From 735e4f8ed6a63ec5ce786f1711f9de91fd7283d8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 22 Feb 2017 17:05:22 -0800 Subject: [PATCH 1/8] diplomacy: use HeterogeneousBag instead of Vec This makes it possible for the bundles to have different widths. Previously, we had to widen all the bundles passing through a node to the widest of all the possibilities. This would mean that if you had two source[] fields, they end up the same. --- src/main/scala/diplomacy/Nodes.scala | 21 ++++++++++--------- src/main/scala/uncore/ahb/Nodes.scala | 4 ++-- .../scala/uncore/ahb/RegisterRouter.scala | 2 +- src/main/scala/uncore/apb/Nodes.scala | 4 ++-- .../scala/uncore/apb/RegisterRouter.scala | 2 +- src/main/scala/uncore/axi4/Nodes.scala | 4 ++-- .../scala/uncore/axi4/RegisterRouter.scala | 2 +- .../scala/uncore/tilelink2/IntNodes.scala | 10 ++------- src/main/scala/uncore/tilelink2/Nodes.scala | 12 +++++------ .../uncore/tilelink2/RegisterRouter.scala | 2 +- 10 files changed, 29 insertions(+), 34 deletions(-) diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index 0796a367..312e9997 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -4,6 +4,7 @@ package diplomacy import Chisel._ import config._ +import util.HeterogeneousBag import scala.collection.mutable.ListBuffer import chisel3.internal.sourceinfo.SourceInfo @@ -14,7 +15,7 @@ import chisel3.internal.sourceinfo.SourceInfo trait InwardNodeImp[DI, UI, EI, BI <: Data] { def edgeI(pd: DI, pu: UI): EI - def bundleI(ei: Seq[EI]): Vec[BI] + def bundleI(ei: EI): BI def colour: String def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => bindings().foreach { case (_, i, o) => i <> o }) @@ -33,7 +34,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data] trait OutwardNodeImp[DO, UO, EO, BO <: Data] { def edgeO(pd: DO, pu: UO): EO - def bundleO(eo: Seq[EO]): Vec[BO] + def bundleO(eo: EO): BO // optional methods to track node graph def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd // insert node into parameters @@ -112,7 +113,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, protected[diplomacy] val iStar: Int protected[diplomacy] val iPortMapping: Seq[(Int, Int)] protected[diplomacy] val iParams: Seq[UI] - val bundleIn: Vec[BI] + val bundleIn: HeterogeneousBag[BI] } trait OutwardNodeHandle[DO, UO, BO <: Data] @@ -145,7 +146,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO protected[diplomacy] val oStar: Int protected[diplomacy] val oPortMapping: Seq[(Int, Int)] protected[diplomacy] val oParams: Seq[DO] - val bundleOut: Vec[BO] + val bundleOut: HeterogeneousBag[BO] } abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( @@ -218,14 +219,14 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( lazy val externalEdgesIn = if (externalIn) {edgesIn} else { Seq() } val flip = false // needed for blind nodes - private def flipO(b: Vec[BO]) = if (flip) b.flip else b - private def flipI(b: Vec[BI]) = if (flip) b else b.flip + private def flipO(b: HeterogeneousBag[BO]) = if (flip) b.flip else b + private def flipI(b: HeterogeneousBag[BI]) = if (flip) b else b.flip val wire = false // needed if you want to grab access to from inside a module - private def wireO(b: Vec[BO]) = if (wire) Wire(b) else b - private def wireI(b: Vec[BI]) = if (wire) Wire(b) else b + private def wireO(b: HeterogeneousBag[BO]) = if (wire) Wire(b) else b + private def wireI(b: HeterogeneousBag[BI]) = if (wire) Wire(b) else b - lazy val bundleOut = wireO(flipO(outer.bundleO(edgesOut))) - lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn))) + lazy val bundleOut = wireO(flipO(HeterogeneousBag(edgesOut.map(outer.bundleO(_))))) + lazy val bundleIn = wireI(flipI(HeterogeneousBag(edgesIn .map(inner.bundleI(_))))) // connects the outward part of a node with the inward part of this node private def bind(h: OutwardNodeHandle[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = { diff --git a/src/main/scala/uncore/ahb/Nodes.scala b/src/main/scala/uncore/ahb/Nodes.scala index 50843943..d50d62f9 100644 --- a/src/main/scala/uncore/ahb/Nodes.scala +++ b/src/main/scala/uncore/ahb/Nodes.scala @@ -12,8 +12,8 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) - def bundleO(eo: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(eo.size, AHBBundle(AHBBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(ei.size, AHBBundle(AHBBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle) + def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/ahb/RegisterRouter.scala b/src/main/scala/uncore/ahb/RegisterRouter.scala index 034df6c8..e514292e 100644 --- a/src/main/scala/uncore/ahb/RegisterRouter.scala +++ b/src/main/scala/uncore/ahb/RegisterRouter.scala @@ -80,7 +80,7 @@ abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concu val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class AHBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AHBBundle])(implicit val p: Parameters) +case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters) class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/apb/Nodes.scala b/src/main/scala/uncore/apb/Nodes.scala index 999d23b2..c7d5fa7d 100644 --- a/src/main/scala/uncore/apb/Nodes.scala +++ b/src/main/scala/uncore/apb/Nodes.scala @@ -12,8 +12,8 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) - def bundleO(eo: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(eo.size, APBBundle(APBBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(ei.size, APBBundle(APBBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle) + def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: APBEdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/apb/RegisterRouter.scala b/src/main/scala/uncore/apb/RegisterRouter.scala index 2f8bfa86..62585d0e 100644 --- a/src/main/scala/uncore/apb/RegisterRouter.scala +++ b/src/main/scala/uncore/apb/RegisterRouter.scala @@ -64,7 +64,7 @@ abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concu val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class APBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[APBBundle])(implicit val p: Parameters) +case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters) class APBRegBundleBase(arg: APBRegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/axi4/Nodes.scala b/src/main/scala/uncore/axi4/Nodes.scala index fafe4c62..a4e1ca00 100644 --- a/src/main/scala/uncore/axi4/Nodes.scala +++ b/src/main/scala/uncore/axi4/Nodes.scala @@ -12,8 +12,8 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu) def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu) - def bundleO(eo: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(eo.size, AXI4Bundle(AXI4BundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(ei.size, AXI4Bundle(AXI4BundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle) + def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index 326f65eb..2da706bf 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -85,7 +85,7 @@ abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, conc val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters) +case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters) class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index ddfa56e1..e83b3936 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -53,14 +53,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In { def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu) def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu) - def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = { - if (eo.isEmpty) Vec(0, Vec(0, Bool())) else - Vec(eo.size, Vec(eo.map(_.source.num).max, Bool())) - } - def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = { - if (ei.isEmpty) Vec(0, Vec(0, Bool())) else - Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())) - } + def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool()) + def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool()) def colour = "#0000ff" // blue override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 22701f12..23b50e01 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -18,8 +18,8 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu) def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu) - def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = Vec(eo.size, TLBundle(TLBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = Vec(ei.size, TLBundle(TLBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle) + def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle) def colour = "#000000" // black override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString @@ -156,8 +156,8 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu) def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu) - def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(eo.size, new TLAsyncBundle(TLAsyncBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(ei.size, new TLAsyncBundle(TLAsyncBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle) + def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle) def colour = "#ff0000" // red override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString @@ -188,8 +188,8 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) - def bundleO(eo: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle) + def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle) def colour = "#00ff00" // green diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 2faa08dc..fc834c6d 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -86,7 +86,7 @@ abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, co val intnode = IntSourceNode(interrupts) } -case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters) +case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters) class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle { From c01aec925922077a475329e10ee13f96d3d6c64e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 22 Feb 2017 18:41:06 -0800 Subject: [PATCH 2/8] tilelink2: support unused IntXing --- src/main/scala/uncore/tilelink2/IntNodes.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index e83b3936..dab03d4e 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -126,6 +126,8 @@ class IntXing()(implicit p: Parameters) extends LazyModule val out = intnode.bundleOut } - io.out := RegNext(RegNext(RegNext(io.in))) + (io.in zip io.out) foreach { case (in, out) => + out := RegNext(RegNext(RegNext(in))) + } } } From 6c3011d513c035bd58825420467aa0dfeaf266dc Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 23 Feb 2017 11:48:49 -0800 Subject: [PATCH 3/8] periphery: make external interrupts a UInt rather than a Vec[Bool] --- src/main/scala/rocketchip/Periphery.scala | 6 ++++-- src/main/scala/rocketchip/TestHarness.scala | 3 +-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 0181cf62..b504839f 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -48,7 +48,8 @@ trait HasPeripheryParameters { trait PeripheryExtInterrupts { this: TopNetwork => - val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts)) + val nExtInterrupts = p(NExtTopInterrupts) + val extInterrupts = IntInternalInputNode(nExtInterrupts) val extInterruptXing = LazyModule(new IntXing) intBus.intnode := extInterruptXing.intnode @@ -59,7 +60,7 @@ trait PeripheryExtInterruptsBundle { this: TopNetworkBundle { val outer: PeripheryExtInterrupts } => - val interrupts = outer.extInterrupts.bundleIn + val interrupts = UInt(INPUT, width = outer.nExtInterrupts) } trait PeripheryExtInterruptsModule { @@ -67,6 +68,7 @@ trait PeripheryExtInterruptsModule { val outer: PeripheryExtInterrupts val io: PeripheryExtInterruptsBundle } => + outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) } } ///// diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index f9569534..ab7126b4 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -15,8 +15,7 @@ class TestHarness()(implicit p: Parameters) extends Module { } val dut = Module(LazyModule(new ExampleRocketTop).module) - for (int <- dut.io.interrupts(0)) - int := Bool(false) + dut.io.interrupts := UInt(0) val channels = p(coreplex.BankedL2Config).nMemoryChannels if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4 From a281ad8ad232f770dd051eddf955e505f275ef58 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 23 Feb 2017 14:25:17 -0800 Subject: [PATCH 4/8] rocketchip: rename some periphery ports --- chisel3 | 2 +- firrtl | 2 +- src/main/scala/rocketchip/BaseTop.scala | 40 +++++---- src/main/scala/rocketchip/Periphery.scala | 85 ++++++++++--------- src/main/scala/rocketchip/RISCVPlatform.scala | 30 +++---- .../scala/rocketchip/RocketPlexMaster.scala | 8 +- src/main/scala/rocketchip/TestHarness.scala | 2 +- 7 files changed, 87 insertions(+), 82 deletions(-) diff --git a/chisel3 b/chisel3 index 50db343d..3ef63639 160000 --- a/chisel3 +++ b/chisel3 @@ -1 +1 @@ -Subproject commit 50db343d5192cd39fa5786e217517c2f139cda64 +Subproject commit 3ef63639284b2b56f415e1540c58d85d88c360db diff --git a/firrtl b/firrtl index b69e787c..568f25b2 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit b69e787c0a698b7fb703ccd8d24003f83207e296 +Subproject commit 568f25b221884eeb0db362c902c933f734c7e47e diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index b5a8c582..7e2638d3 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -12,6 +12,7 @@ import uncore.devices._ import util._ import rocket._ +/** BareTop is the root class for creating a top-level RTL module */ abstract class BareTop(implicit p: Parameters) extends LazyModule { ElaborationArtefacts.add("graphml", graphML) } @@ -26,17 +27,20 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _ val io = _io () } -/** Base Top with no Periphery */ -trait TopNetwork extends HasPeripheryParameters { - val module: TopNetworkModule +/** HasTopLevelNetworks provides buses that will serve as attachment points, + * for use in sub-traits that connect individual agents or external ports. + */ +trait HasTopLevelNetworks extends HasPeripheryParameters { + val module: HasTopLevelNetworksModule - // Add a SoC and peripheral bus - val socBus = LazyModule(new TLXbar) - val peripheryBus = LazyModule(new TLXbar) - val intBus = LazyModule(new IntXbar) - val l2 = LazyModule(new TLBuffer) - val mem = Seq.fill(p(coreplex.BankedL2Config).nMemoryChannels) { LazyModule(new TLXbar) } + val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH) + val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL) + val intBus = LazyModule(new IntXbar) // Interrupts + val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2 + val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM + // The peripheryBus hangs off of socBus; + // here we convert TL-UH -> TL-UL peripheryBus.node := TLBuffer()( TLWidthWidget(socBusConfig.beatBytes)( @@ -44,23 +48,23 @@ trait TopNetwork extends HasPeripheryParameters { socBus.node))) } -trait TopNetworkBundle extends HasPeripheryParameters { - val outer: TopNetwork +trait HasTopLevelNetworksBundle extends HasPeripheryParameters { + val outer: HasTopLevelNetworks } -trait TopNetworkModule extends HasPeripheryParameters { - val io: TopNetworkBundle - val outer: TopNetwork +trait HasTopLevelNetworksModule extends HasPeripheryParameters { + val outer: HasTopLevelNetworks + val io: HasTopLevelNetworksBundle } -/** Base Top with no Periphery */ +/** Base Top class with no peripheral devices or ports added */ class BaseTop(implicit p: Parameters) extends BareTop - with TopNetwork { + with HasTopLevelNetworks { override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this)) } class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer) - with TopNetworkBundle + with HasTopLevelNetworksBundle class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) - with TopNetworkModule + with HasTopLevelNetworksModule diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index b504839f..e495ef33 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -37,16 +37,17 @@ case object ZeroConfig extends Field[ZeroConfig] /** Utility trait for quick access to some relevant parameters */ trait HasPeripheryParameters { implicit val p: Parameters - lazy val peripheryBusConfig = p(PeripheryBusConfig) - lazy val socBusConfig = p(SOCBusConfig) - lazy val cacheBlockBytes = p(CacheBlockBytes) - lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic) + def peripheryBusConfig = p(PeripheryBusConfig) + def socBusConfig = p(SOCBusConfig) + def cacheBlockBytes = p(CacheBlockBytes) + def peripheryBusArithmetic = p(PeripheryBusArithmetic) + def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels } ///// trait PeripheryExtInterrupts { - this: TopNetwork => + this: HasTopLevelNetworks => val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntInternalInputNode(nExtInterrupts) @@ -57,14 +58,14 @@ trait PeripheryExtInterrupts { } trait PeripheryExtInterruptsBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryExtInterrupts } => val interrupts = UInt(INPUT, width = outer.nExtInterrupts) } trait PeripheryExtInterruptsModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryExtInterrupts val io: PeripheryExtInterruptsBundle } => @@ -74,7 +75,7 @@ trait PeripheryExtInterruptsModule { ///// trait PeripheryMasterAXI4Mem { - this: TopNetwork => + this: HasTopLevelNetworks => val module: PeripheryMasterAXI4MemModule private val config = p(ExtMem) @@ -107,14 +108,14 @@ trait PeripheryMasterAXI4Mem { } trait PeripheryMasterAXI4MemBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterAXI4Mem } => val mem_axi4 = outer.mem_axi4.bundleOut } trait PeripheryMasterAXI4MemModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterAXI4Mem val io: PeripheryMasterAXI4MemBundle } => @@ -123,7 +124,7 @@ trait PeripheryMasterAXI4MemModule { ///// trait PeripheryZero { - this: TopNetwork => + this: HasTopLevelNetworks => val module: PeripheryZeroModule private val config = p(ZeroConfig) @@ -138,13 +139,13 @@ trait PeripheryZero { } trait PeripheryZeroBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryZero } => } trait PeripheryZeroModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryZero val io: PeripheryZeroBundle } => @@ -154,7 +155,7 @@ trait PeripheryZeroModule { // PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one. trait PeripheryMasterAXI4MMIO { - this: TopNetwork => + this: HasTopLevelNetworks => private val config = p(ExtBus) val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters( @@ -175,14 +176,14 @@ trait PeripheryMasterAXI4MMIO { } trait PeripheryMasterAXI4MMIOBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterAXI4MMIO } => val mmio_axi4 = outer.mmio_axi4.bundleOut } trait PeripheryMasterAXI4MMIOModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterAXI4MMIO val io: PeripheryMasterAXI4MMIOBundle } => @@ -192,26 +193,26 @@ trait PeripheryMasterAXI4MMIOModule { ///// // PeripherySlaveAXI4 is an example, make your own cake pattern like this one. -trait PeripherySlaveAXI4 extends TopNetwork { +trait PeripherySlaveAXI4 extends HasTopLevelNetworks { private val config = p(ExtIn) - val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( + val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( masters = Seq(AXI4MasterParameters( id = IdRange(0, 1 << config.idBits)))))) - l2.node := + l2FrontendBus.node := TLSourceShrinker(1 << config.sourceBits)( TLWidthWidget(config.beatBytes)( AXI4ToTL()( AXI4Fragmenter()( - l2_axi4)))) + l2FrontendAXI4Node)))) } -trait PeripherySlaveAXI4Bundle extends TopNetworkBundle { +trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle { val outer: PeripherySlaveAXI4 - val l2_axi4 = outer.l2_axi4.bundleIn + val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn } -trait PeripherySlaveAXI4Module extends TopNetworkModule { +trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule { val outer: PeripherySlaveAXI4 val io: PeripherySlaveAXI4Bundle // nothing to do @@ -221,7 +222,7 @@ trait PeripherySlaveAXI4Module extends TopNetworkModule { // Add an external TL-UL slave trait PeripheryMasterTLMMIO { - this: TopNetwork => + this: HasTopLevelNetworks => private val config = p(ExtBus) val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters( @@ -241,14 +242,14 @@ trait PeripheryMasterTLMMIO { } trait PeripheryMasterTLMMIOBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterTLMMIO } => val mmio_tl = outer.mmio_tl.bundleOut } trait PeripheryMasterTLMMIOModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterTLMMIO val io: PeripheryMasterTLMMIOBundle } => @@ -258,24 +259,24 @@ trait PeripheryMasterTLMMIOModule { ///// // NOTE: this port is NOT allowed to issue Acquires -trait PeripherySlaveTL extends TopNetwork { +trait PeripherySlaveTL extends HasTopLevelNetworks { private val config = p(ExtIn) - val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters( + val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters( clients = Seq(TLClientParameters( sourceId = IdRange(0, 1 << config.idBits)))))) - l2.node := + l2FrontendBus.node := TLSourceShrinker(1 << config.sourceBits)( TLWidthWidget(config.beatBytes)( - l2_tl)) + l2FrontendTLNode)) } -trait PeripherySlaveTLBundle extends TopNetworkBundle { +trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle { val outer: PeripherySlaveTL - val l2_tl = outer.l2_tl.bundleIn + val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn } -trait PeripherySlaveTLModule extends TopNetworkModule { +trait PeripherySlaveTLModule extends HasTopLevelNetworksModule { val outer: PeripherySlaveTL val io: PeripherySlaveTLBundle // nothing to do @@ -284,7 +285,7 @@ trait PeripherySlaveTLModule extends TopNetworkModule { ///// trait PeripheryBootROM { - this: TopNetwork => + this: HasTopLevelNetworks => val coreplex: CoreplexRISCVPlatform private val bootrom_address = 0x1000 @@ -295,13 +296,13 @@ trait PeripheryBootROM { } trait PeripheryBootROMBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryBootROM } => } trait PeripheryBootROMModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryBootROM val io: PeripheryBootROMBundle } => @@ -310,20 +311,20 @@ trait PeripheryBootROMModule { ///// trait PeripheryTestRAM { - this: TopNetwork => + this: HasTopLevelNetworks => val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes)) testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) } trait PeripheryTestRAMBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryTestRAM } => } trait PeripheryTestRAMModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryTestRAM val io: PeripheryTestRAMBundle } => @@ -332,19 +333,19 @@ trait PeripheryTestRAMModule { ///// trait PeripheryTestBusMaster { - this: TopNetwork => + this: HasTopLevelNetworks => val fuzzer = LazyModule(new TLFuzzer(5000)) peripheryBus.node := fuzzer.node } trait PeripheryTestBusMasterBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryTestBusMaster } => } trait PeripheryTestBusMasterModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryTestBusMaster val io: PeripheryTestBusMasterBundle } => diff --git a/src/main/scala/rocketchip/RISCVPlatform.scala b/src/main/scala/rocketchip/RISCVPlatform.scala index 35aae1fc..7bc9779a 100644 --- a/src/main/scala/rocketchip/RISCVPlatform.scala +++ b/src/main/scala/rocketchip/RISCVPlatform.scala @@ -13,18 +13,18 @@ import coreplex._ /// Core with JTAG for debug only -trait PeripheryJTAG extends TopNetwork { +trait PeripheryJTAG extends HasTopLevelNetworks { val module: PeripheryJTAGModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryJTAGBundle extends TopNetworkBundle { +trait PeripheryJTAGBundle extends HasTopLevelNetworksBundle { val outer: PeripheryJTAG val jtag = new JTAGIO(true).flip } -trait PeripheryJTAGModule extends TopNetworkModule { +trait PeripheryJTAGModule extends HasTopLevelNetworksModule { val outer: PeripheryJTAG val io: PeripheryJTAGBundle @@ -38,18 +38,18 @@ trait PeripheryJTAGModule extends TopNetworkModule { /// Core with DTM for debug only -trait PeripheryDTM extends TopNetwork { +trait PeripheryDTM extends HasTopLevelNetworks { val module: PeripheryDTMModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryDTMBundle extends TopNetworkBundle { +trait PeripheryDTMBundle extends HasTopLevelNetworksBundle { val outer: PeripheryDTM val debug = new DebugBusIO().flip } -trait PeripheryDTMModule extends TopNetworkModule { +trait PeripheryDTMModule extends HasTopLevelNetworksModule { val outer: PeripheryDTM val io: PeripheryDTMBundle @@ -58,19 +58,19 @@ trait PeripheryDTMModule extends TopNetworkModule { /// Core with DTM or JTAG based on a parameter -trait PeripheryDebug extends TopNetwork { +trait PeripheryDebug extends HasTopLevelNetworks { val module: PeripheryDebugModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryDebugBundle extends TopNetworkBundle { +trait PeripheryDebugBundle extends HasTopLevelNetworksBundle { val outer: PeripheryDebug val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip) val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip) } -trait PeripheryDebugModule extends TopNetworkModule { +trait PeripheryDebugModule extends HasTopLevelNetworksModule { val outer: PeripheryDebug val io: PeripheryDebugBundle @@ -86,16 +86,16 @@ trait PeripheryDebugModule extends TopNetworkModule { /// Real-time clock is based on RTCPeriod relative to Top clock -trait PeripheryCounter extends TopNetwork { +trait PeripheryCounter extends HasTopLevelNetworks { val module: PeripheryCounterModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryCounterBundle extends TopNetworkBundle { +trait PeripheryCounterBundle extends HasTopLevelNetworksBundle { val outer: PeripheryCounter } -trait PeripheryCounterModule extends TopNetworkModule { +trait PeripheryCounterModule extends HasTopLevelNetworksModule { val outer: PeripheryCounter val io: PeripheryCounterBundle @@ -111,16 +111,16 @@ trait PeripheryCounterModule extends TopNetworkModule { /// Coreplex will power-on running at 0x1000 (BootROM) -trait HardwiredResetVector extends TopNetwork { +trait HardwiredResetVector extends HasTopLevelNetworks { val module: HardwiredResetVectorModule val coreplex: CoreplexRISCVPlatform } -trait HardwiredResetVectorBundle extends TopNetworkBundle { +trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle { val outer: HardwiredResetVector } -trait HardwiredResetVectorModule extends TopNetworkModule { +trait HardwiredResetVectorModule extends HasTopLevelNetworksModule { val outer: HardwiredResetVector val io: HardwiredResetVectorBundle diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala index 06591dbb..8d2bf546 100644 --- a/src/main/scala/rocketchip/RocketPlexMaster.scala +++ b/src/main/scala/rocketchip/RocketPlexMaster.scala @@ -10,12 +10,12 @@ import uncore.devices._ import util._ import coreplex._ -trait RocketPlexMaster extends TopNetwork { +trait RocketPlexMaster extends HasTopLevelNetworks { val module: RocketPlexMasterModule val coreplex = LazyModule(new DefaultCoreplex) - coreplex.l2in :=* l2.node + coreplex.l2in :=* l2FrontendBus.node socBus.node := coreplex.mmio coreplex.mmioInt := intBus.intnode @@ -23,11 +23,11 @@ trait RocketPlexMaster extends TopNetwork { (mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel } } -trait RocketPlexMasterBundle extends TopNetworkBundle { +trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle { val outer: RocketPlexMaster } -trait RocketPlexMasterModule extends TopNetworkModule { +trait RocketPlexMasterModule extends HasTopLevelNetworksModule { val outer: RocketPlexMaster val io: RocketPlexMasterBundle val clock: Clock diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index ab7126b4..3d50bed5 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -29,7 +29,7 @@ class TestHarness()(implicit p: Parameters) extends Module { val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module) mmio_sim.io.axi4 <> dut.io.mmio_axi4 - val l2_axi4 = dut.io.l2_axi4(0) + val l2_axi4 = dut.io.l2_frontend_bus_axi4(0) l2_axi4.ar.valid := Bool(false) l2_axi4.aw.valid := Bool(false) l2_axi4.w .valid := Bool(false) From 62f5727bc677b4986b6a3d3f33111fb2cf5645c9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 27 Feb 2017 19:19:41 -0800 Subject: [PATCH 5/8] periphery: peripheryBusBytes and socBusBytes --- src/main/scala/rocketchip/Periphery.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index e495ef33..d8d4aae5 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -38,7 +38,9 @@ case object ZeroConfig extends Field[ZeroConfig] trait HasPeripheryParameters { implicit val p: Parameters def peripheryBusConfig = p(PeripheryBusConfig) + def peripheryBusBytes = peripheryBusConfig.beatBytes def socBusConfig = p(SOCBusConfig) + def socBusBytes = socBusConfig.beatBytes def cacheBlockBytes = p(CacheBlockBytes) def peripheryBusArithmetic = p(PeripheryBusArithmetic) def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels From 9bfcb40cb4f1b7fd1adf6014f30cb55f040242f0 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 27 Feb 2017 20:18:28 -0800 Subject: [PATCH 6/8] util: Majority on sets of bools --- src/main/scala/util/Misc.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index 006aa696..55dc1ed0 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -160,3 +160,15 @@ object Random private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < UInt(round((i << value.getWidth).toDouble / slices))) } + +object Majority { + def apply(in: Set[Bool]): Bool = { + val n = (in.size >> 1) + 1 + val clauses = in.subsets(n).map(_.reduce(_ && _)) + clauses.reduce(_ || _) + } + + def apply(in: Seq[Bool]): Bool = apply(in.toSet) + + def apply(in: UInt): Bool = apply(in.toBools.toSet) +} From 9ce6898d469b8403b076473146e38c68ea632f7b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 1 Mar 2017 16:58:29 -0800 Subject: [PATCH 7/8] firrtl: bump firrtl --- firrtl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firrtl b/firrtl index 8528ba76..7f280a5b 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit 8528ba768003a359bf6c40d2fdc102c4a0d6bea7 +Subproject commit 7f280a5b0821c61284e9bf9ed7780cc825f7f3e8 From 9544b8007e7102b029c74edafd4f0f17a7b1bb64 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 2 Mar 2017 10:41:26 -0800 Subject: [PATCH 8/8] bump chisel3 --- chisel3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel3 b/chisel3 index cae110e0..3e6ef13f 160000 --- a/chisel3 +++ b/chisel3 @@ -1 +1 @@ -Subproject commit cae110e06d7dfb206e6d50565ee25221b8c6d0a5 +Subproject commit 3e6ef13ff5cda2e65efbbf5d306cc101582ad0e5