riscv/rocket-chip
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Merge pull request #1122 from freechipsproject/fix-itim

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Fix ITIM deallocation during I$ refill causing data corruption
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Andrew Waterman 2017-11-20 15:08:25 -08:00 committed by GitHub
commit 39f1acfd34
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1 changed files with 13 additions and 2 deletions
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15
src/main/scala/rocket/ICache.scala
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@ -225,7 +225,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr)) val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr) && lineInScratchpad(scratchpadLine(s1s3_slaveAddr))) val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
Mux(s3_slaveValid, row(s1s3_slaveAddr), Mux(s3_slaveValid, row(s1s3_slaveAddr),
Mux(s0_slaveValid, row(s0_slaveAddr), Mux(s0_slaveValid, row(s0_slaveAddr),
@ -294,9 +294,20 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val enable = scratchpadWayValid(scratchpadWay(a.address)) val enable = scratchpadWayValid(scratchpadWay(a.address))
when (!lineInScratchpad(scratchpadLine(a.address))) { when (!lineInScratchpad(scratchpadLine(a.address))) {
scratchpadMax.get := scratchpadLine(a.address) scratchpadMax.get := scratchpadLine(a.address)
when (enable) { invalidate := true } invalidate := true
} }
scratchpadOn := enable scratchpadOn := enable
val itim_allocated = !scratchpadOn && enable
val itim_deallocated = scratchpadOn && !enable
val itim_increase = scratchpadOn && enable && scratchpadLine(a.address) > scratchpadMax.get
val refilling = refill_valid && refill_cnt > 0
ccover(itim_allocated, "ITIM_ALLOCATE", "ITIM allocated")
ccover(itim_allocated && refilling, "ITIM_ALLOCATE_WHILE_REFILL", "ITIM allocated while I$ refill")
ccover(itim_deallocated, "ITIM_DEALLOCATE", "ITIM deallocated")
ccover(itim_deallocated && refilling, "ITIM_DEALLOCATE_WHILE_REFILL", "ITIM deallocated while I$ refill")
ccover(itim_increase, "ITIM_SIZE_INCREASE", "ITIM size increased")
ccover(itim_increase && refilling, "ITIM_SIZE_INCREASE_WHILE_REFILL", "ITIM size increased while I$ refill")
} }
} }