From 66b7a8a5ed420c55001907a9cc8541627e85ba56 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 20 Nov 2017 12:26:04 -0800 Subject: [PATCH 1/3] Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" This reverts commit 3db066303b16f6ac6688cdc2f48d7ff066e4b52b. --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index a03c21d8..c5b5cdd8 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -225,7 +225,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr)) - val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr) && lineInScratchpad(scratchpadLine(s1s3_slaveAddr))) + val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr)) val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, Mux(s3_slaveValid, row(s1s3_slaveAddr), Mux(s0_slaveValid, row(s0_slaveAddr), From 5e94884f096c55d56db7988bbab8cfd83ea45035 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 20 Nov 2017 12:30:40 -0800 Subject: [PATCH 2/3] Fix ITIM deallocation during I$ refill causing data corruption Deallocation can change repl_way, which violates the assumption that it remains constant throughout refill. The workaround described in commit 3db066303b16f6ac6688cdc2f48d7ff066e4b52b still suffices, provided only the hart that owns the ITIM changes the ITIM allocation. This subsumes commit 3db066303b16f6ac6688cdc2f48d7ff066e4b52b. --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index c5b5cdd8..a922280a 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -294,7 +294,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val enable = scratchpadWayValid(scratchpadWay(a.address)) when (!lineInScratchpad(scratchpadLine(a.address))) { scratchpadMax.get := scratchpadLine(a.address) - when (enable) { invalidate := true } + invalidate := true } scratchpadOn := enable } From a60d7d419da2b0a9ad902bd4d2a7407fc0950d89 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 20 Nov 2017 13:05:44 -0800 Subject: [PATCH 3/3] icache: add a couple cover points for I$ and ITIM iteraction --- src/main/scala/rocket/ICache.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index a922280a..426bcbfa 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -297,6 +297,17 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) invalidate := true } scratchpadOn := enable + + val itim_allocated = !scratchpadOn && enable + val itim_deallocated = scratchpadOn && !enable + val itim_increase = scratchpadOn && enable && scratchpadLine(a.address) > scratchpadMax.get + val refilling = refill_valid && refill_cnt > 0 + ccover(itim_allocated, "ITIM_ALLOCATE", "ITIM allocated") + ccover(itim_allocated && refilling, "ITIM_ALLOCATE_WHILE_REFILL", "ITIM allocated while I$ refill") + ccover(itim_deallocated, "ITIM_DEALLOCATE", "ITIM deallocated") + ccover(itim_deallocated && refilling, "ITIM_DEALLOCATE_WHILE_REFILL", "ITIM deallocated while I$ refill") + ccover(itim_increase, "ITIM_SIZE_INCREASE", "ITIM size increased") + ccover(itim_increase && refilling, "ITIM_SIZE_INCREASE_WHILE_REFILL", "ITIM size increased while I$ refill") } }