riscv/rocket-chip
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refactor MemIO to not use params

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This commit is contained in:
Henry Cook
2015-10-02 15:38:14 -07:00
parent 3d10a89907
commit 38ae2707a3
3 changed files with 5 additions and 5 deletions
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6
src/main/scala/Vlsi.scala
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@ -6,9 +6,9 @@ import Chisel._
import junctions._
import uncore._
class MemDessert extends Module {
val io = new MemDesserIO(params(HTIFWidth))
val x = Module(new MemDesser(params(HTIFWidth)))
class MemDessert(implicit val p: Parameters) extends Module {
val io = new MemDesserIO(p(HTIFWidth))
val x = Module(new MemDesser(p(HTIFWidth)))
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}