diff --git a/junctions b/junctions
index 52be2a2c..372e8057 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit 52be2a2c019931de304c5701e694f243ef018e75
+Subproject commit 372e80574bc42d8b623f69b2d5bd995aa5d0a759
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 3e5762d1..2a14a7dd 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -60,7 +60,7 @@ class BasicTopIO extends Bundle {
   val mem_backup_ctrl = new MemBackupCtrlIO
 }
 
-class TopIO extends BasicTopIO {
+class TopIO(implicit val p: Parameters) extends BasicTopIO {
   val mem = new MemIO
 }
 
diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala
index 27a60013..c64730e0 100644
--- a/src/main/scala/Vlsi.scala
+++ b/src/main/scala/Vlsi.scala
@@ -6,9 +6,9 @@ import Chisel._
 import junctions._
 import uncore._
 
-class MemDessert extends Module {
-  val io = new MemDesserIO(params(HTIFWidth))
-  val x = Module(new MemDesser(params(HTIFWidth)))
+class MemDessert(implicit val p: Parameters) extends Module {
+  val io = new MemDesserIO(p(HTIFWidth))
+  val x = Module(new MemDesser(p(HTIFWidth)))
   io.narrow <> x.io.narrow
   io.wide <> x.io.wide
 }