riscv/rocket-chip
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don't use reset combinationally

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This commit is contained in:
Andrew Waterman 2013-01-24 17:46:11 -08:00
parent bb6fbddf1f
commit 37ee843b2c
1 changed files with 5 additions and 2 deletions
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7
rocket/src/main/scala/nbdcache.scala
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@ -508,7 +508,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
val line_state = UFix(INPUT, 2) val line_state = UFix(INPUT, 2)
} }
val s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(8) { UFix() } val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(9) { UFix() }
val state = Reg(resetVal = s_invalid) val state = Reg(resetVal = s_invalid)
val line_state = Reg() { UFix() } val line_state = Reg() { UFix() }
val way_en = Reg() { Bits() } val way_en = Reg() { Bits() }
@ -546,8 +546,11 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
state := s_meta_read state := s_meta_read
req := io.req.bits req := io.req.bits
} }
when (state === s_reset) {
state := s_invalid
}
io.req.ready := state === s_invalid && !reset io.req.ready := state === s_invalid
io.rep.valid := state === s_release io.rep.valid := state === s_release
io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush)) io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush))