rocketchip: move from using cde to config

src/main/scala/coreplex/BaseCoreplex.scala

@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._

src/main/scala/coreplex/Configs.scala

@@ -15,7 +15,7 @@ import rocket._
 import util._
 import util.ConfigUtils._
 import rocketchip.{GlobalAddrMap}
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 
 class BaseCoreplexConfig extends Config (
   { (pname,site,here) =>

src/main/scala/coreplex/Coreplex.scala

@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._

src/main/scala/coreplex/RISCVPlatform.scala

@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._

src/main/scala/coreplex/RocketPlex.scala

@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import diplomacy._
 import uncore.tilelink2._
 import uncore.coherence._

src/main/scala/groundtest/BusMasterTest.scala

@@ -7,7 +7,7 @@ import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
 import junctions.HasAddrMapParameters
 import rocketchip._
-import cde.Parameters
+import config._
 
 /**
  * An example bus mastering devices that writes some preset data to memory.

src/main/scala/groundtest/CacheFillTest.scala

@@ -5,7 +5,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
     with HasTileLinkParameters {

src/main/scala/groundtest/Comparator.scala

@@ -7,7 +7,7 @@ import junctions._
 import rocket._
 import util.Timer
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 case class ComparatorParameters(
   targets:    Seq[Long], 

src/main/scala/groundtest/Configs.scala

@@ -8,7 +8,7 @@ import uncore.coherence._
 import uncore.agents._
 import uncore.devices.NTiles
 import junctions._
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 import scala.math.max
 import coreplex._
 import rocketchip._

src/main/scala/groundtest/Coreplex.scala

@@ -1,7 +1,7 @@
 package groundtest
 
 import Chisel._
-import cde.Parameters
+import config._
 import diplomacy._
 import coreplex._
 import uncore.devices.NTiles

src/main/scala/groundtest/Regression.scala

@@ -8,7 +8,7 @@ import util._
 import junctions.HasAddrMapParameters
 import rocket._
 import rocketchip._
-import cde.{Parameters, Field}
+import config._
 
 class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
   val start = Bool(INPUT)

src/main/scala/groundtest/TestHarness.scala

@@ -2,7 +2,7 @@ package groundtest
 
 import Chisel._
 import diplomacy._
-import cde.Parameters
+import config._
 import rocketchip._
 import util._
 

src/main/scala/groundtest/Tile.scala

@@ -11,7 +11,7 @@ import scala.util.Random
 import scala.collection.mutable.ListBuffer
 import junctions.HasAddrMapParameters
 import util.ParameterizedBundle
-import cde.{Parameters, Field}
+import config._
 
 case object BuildGroundTest extends Field[Parameters => GroundTest]
 

src/main/scala/groundtest/Top.scala

@@ -1,7 +1,7 @@
 package groundtest
 
 import Chisel._
-import cde.Parameters
+import config._
 import diplomacy._
 import coreplex._
 import rocketchip._

src/main/scala/groundtest/TraceGen.scala

@@ -24,7 +24,7 @@ import junctions._
 import rocket._
 import util.{Timer, DynamicTimer}
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 // =======
 // Outline

src/main/scala/groundtest/TrafficGenerator.scala

@@ -8,7 +8,7 @@ import junctions._
 import rocket._
 import util.SimpleTimer
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 case class TrafficGeneratorParameters(
   maxRequests: Int,

src/main/scala/junctions/NastiDriver.scala

@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
     (implicit p: Parameters) extends NastiModule {

src/main/scala/junctions/addrmap.scala

@@ -3,7 +3,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import scala.collection.mutable.HashMap
 
 case object PAddrBits extends Field[Int]

src/main/scala/junctions/hasti.scala

@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import unittest.UnitTest
 import util.ParameterizedBundle
 

src/main/scala/junctions/jtag.scala

@@ -1,6 +1,6 @@
 package junctions
 import Chisel._
-import cde.{Parameters}
+import config._
 
 class JTAGIO(drvTdo: Boolean = false) extends Bundle {
   val TCK = Clock(OUTPUT)

src/main/scala/junctions/nasti.scala

@@ -5,7 +5,7 @@ import Chisel._
 import scala.math.max
 import scala.collection.mutable.ArraySeq
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case object NastiKey extends Field[NastiParameters]
 

src/main/scala/junctions/poci.scala

@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 
 class PociIO(implicit p: Parameters) extends HastiBundle()(p)
 {

src/main/scala/junctions/stream.scala

@@ -2,7 +2,7 @@ package junctions
 
 import Chisel._
 import NastiConstants._
-import cde.Parameters
+import config._
 
 class StreamChannel(w: Int) extends Bundle {
   val data = UInt(width = w)

src/main/scala/rocket/arbiter.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util.{ParameterizedBundle, DecoupledHelper}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module

src/main/scala/rocket/breakpoint.scala

@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.Parameters
+import config._
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
   val ttype = UInt(width = 4)

src/main/scala/rocket/btb.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util._
 import Chisel.ImplicitConversions._
 import uncore.agents.PseudoLRU

src/main/scala/rocket/csr.scala

@@ -4,7 +4,7 @@ package rocket
 
 import Chisel._
 import Instructions._
-import cde.{Parameters, Field}
+import config._
 import uncore.devices._
 import util._
 import Chisel.ImplicitConversions._

src/main/scala/rocket/dcache.scala

@@ -12,7 +12,7 @@ import uncore.util._
 import util._
 import TLMessages._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
   val addr = Bits(width = untagBits)

src/main/scala/rocket/dpath_alu.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import Instructions._
 
 object ALU

src/main/scala/rocket/fpu.scala

@@ -8,7 +8,7 @@ import util._
 import Chisel.ImplicitConversions._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
-import cde.{Parameters, Field}
+import config._
 
 case class FPUConfig(
   divSqrt: Boolean = true,

src/main/scala/rocket/frontend.scala

@@ -4,7 +4,7 @@ import Chisel._
 import uncore.tilelink._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)

src/main/scala/rocket/ibuf.scala

@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
   val pf0 = Bool() // page fault on first half of instruction

src/main/scala/rocket/icache.scala

@@ -6,7 +6,7 @@ import uncore.tilelink._
 import uncore.util._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats

src/main/scala/rocket/idecode.scala

@@ -6,7 +6,7 @@ import Chisel._
 import Instructions._
 import uncore.constants.MemoryOpConstants._
 import ALU._
-import cde.Parameters
+import config._
 import util._
 import Chisel.ImplicitConversions._
 

src/main/scala/rocket/nbdcache.scala

@@ -11,7 +11,7 @@ import uncore.util._
 import diplomacy._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case class DCacheConfig(
   nMSHRs: Int = 1,

src/main/scala/rocket/ptw.scala

@@ -7,7 +7,7 @@ import uncore.agents._
 import uncore.constants._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val prv = Bits(width = 2)

src/main/scala/rocket/rocc.scala

@@ -8,7 +8,7 @@ import uncore.constants._
 import uncore.agents.CacheName
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]

src/main/scala/rocket/rocket.scala

@@ -9,7 +9,7 @@ import uncore.constants._
 import junctions.HasAddrMapParameters
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object XLen extends Field[Int]
 case object FetchWidth extends Field[Int]

src/main/scala/rocket/rvc.scala

@@ -3,7 +3,7 @@ package rocket
 import Chisel._
 import Chisel.ImplicitConversions._
 import util._
-import cde.Parameters
+import config._
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(width = 32)

src/main/scala/rocket/tile.scala

@@ -10,7 +10,7 @@ import uncore.agents._
 import uncore.converters._
 import uncore.devices._
 import util._
-import cde.{Parameters, Field}
+import config._
 import scala.collection.mutable.ListBuffer
 
 case object BuildRoCC extends Field[Seq[RoccParameters]]

src/main/scala/rocket/tlb.scala

@@ -7,7 +7,7 @@ import util._
 import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
-import cde.{Parameters, Field}
+import config._
 import uncore.agents._
 import uncore.coherence._
 

src/main/scala/rocketchip/BaseTop.scala

@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._

src/main/scala/rocketchip/Configs.scala

@@ -16,7 +16,7 @@ import scala.math.max
 import scala.collection.mutable.{LinkedHashSet, ListBuffer}
 import scala.collection.immutable.HashMap
 import DefaultTestSuites._
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 
 class BasePlatformConfig extends Config(
   (pname,site,here) => pname match {

src/main/scala/rocketchip/DebugTransport.scala

@@ -4,7 +4,7 @@ import Chisel._
 import uncore.devices._
 import junctions._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case object IncludeJtagDTM extends Field[Boolean]
 

src/main/scala/rocketchip/ExampleTop.scala

@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import coreplex._
 import rocketchip._

src/main/scala/rocketchip/Periphery.scala

@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field, Dump}
+import config._
 import junctions._
 import junctions.NastiConstants._
 import diplomacy._

src/main/scala/rocketchip/RISCVPlatform.scala

@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field, Dump}
+import config._
 import diplomacy._
 import uncore.tilelink2._
 import uncore.devices._

src/main/scala/rocketchip/TestHarness.scala

@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import coreplex._

src/main/scala/rocketchip/Utils.scala

@@ -2,7 +2,7 @@
 
 package rocketchip
 
-import cde.{Parameters, Dump}
+import config._
 import junctions._
 import diplomacy._
 import uncore.devices._

src/main/scala/uncore/Builder.scala

@@ -1,7 +1,7 @@
 package uncore
 
 import Chisel._
-import cde.{Config, Parameters, ParameterDump, Knob, Dump, CDEMatchError}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.agents._

src/main/scala/uncore/agents/Agents.scala

@@ -3,7 +3,7 @@
 package uncore.agents
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.converters._

src/main/scala/uncore/agents/Broadcast.scala

@@ -8,7 +8,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 class L2BroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
 

src/main/scala/uncore/agents/Bufferless.scala

@@ -6,7 +6,7 @@ import Chisel._
 import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 
 
 class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {

src/main/scala/uncore/agents/Cache.scala

@@ -12,7 +12,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case class CacheConfig(
   nSets:         Int,

src/main/scala/uncore/agents/Mmio.scala

@@ -2,7 +2,7 @@ package uncore.agents
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 class MMIOTileLinkManagerData(implicit p: Parameters)
     extends TLBundle()(p)

src/main/scala/uncore/agents/StatelessBridge.scala

@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.devices._
-import cde.{Parameters, Field, Config}
+import config._
 
 /** The ManagerToClientStateless Bridge does not maintain any state for the messages
   *  which pass through it. It simply passes the messages back and forth without any

src/main/scala/uncore/agents/StoreDataQueue.scala

@@ -3,7 +3,7 @@
 package uncore.agents
 import Chisel._
 import uncore.tilelink._
-import cde.{Parameters, Field}
+import config._
 
 case object L2StoreDataQueueDepth extends Field[Int]
 

src/main/scala/uncore/agents/Trackers.scala

@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.util._
 import util._
-import cde.{Field, Parameters}
+import config._
 import scala.math.max
 
 case object EnableL2Logging extends Field[Boolean]

src/main/scala/uncore/coherence/Metadata.scala

@@ -5,7 +5,7 @@ package uncore.coherence
 import Chisel._
 import uncore.tilelink._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 
 /** Identifies the TLId of the inner network in a hierarchical cache controller */ 
 case object InnerTLId extends Field[String]

src/main/scala/uncore/converters/Ahb.scala

@@ -5,7 +5,7 @@ import junctions._
 import uncore.tilelink._
 import uncore.util._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 import HastiConstants._
 
 /* We need to translate TileLink requests into operations we can actually execute on AHB.

src/main/scala/uncore/converters/Nasti.scala

@@ -6,7 +6,7 @@ import util.{ReorderQueue, DecoupledHelper}
 import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class IdMapper(val inIdBits: Int, val outIdBits: Int,

src/main/scala/uncore/converters/Tilelink.scala

@@ -8,7 +8,7 @@ import uncore.util._
 import uncore.constants._
 import uncore.devices.TileLinkTestRAM
 import unittest.UnitTest
-import cde.Parameters
+import config._
 
 /** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
 object TileLinkIOWrapper {

src/main/scala/uncore/devices/Bram.scala

@@ -1,7 +1,7 @@
 package uncore.devices
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import unittest.UnitTest
 import junctions._
 import uncore.tilelink._

src/main/scala/uncore/devices/Debug.scala

@@ -7,7 +7,7 @@ import junctions._
 import util._
 import regmapper._
 import uncore.tilelink2._
-import cde.{Parameters, Config, Field}
+import config._
 
 // *****************************************
 // Constants which are interesting even

src/main/scala/uncore/devices/Plic.scala

@@ -9,7 +9,7 @@ import junctions._
 import diplomacy._
 import regmapper._
 import uncore.tilelink2._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class GatewayPLICIO extends Bundle {

src/main/scala/uncore/devices/Prci.scala

@@ -11,7 +11,7 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 import scala.math.{min,max}
-import cde.{Parameters, Field}
+import config._
 
 /** Number of tiles */
 case object NTiles extends Field[Int]

src/main/scala/uncore/devices/Rom.scala

@@ -7,7 +7,7 @@ import diplomacy._
 import uncore.tilelink._
 import uncore.tilelink2._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {

src/main/scala/uncore/tilelink/Arbiters.scala

@@ -1,7 +1,7 @@
 package uncore.tilelink
 import Chisel._
 import junctions._
-import cde.{Parameters, Field}
+import config._
 
 /** Utility functions for constructing TileLinkIO arbiters */
 trait TileLinkArbiterLike extends HasTileLinkParameters {

src/main/scala/uncore/tilelink/Definitions.scala

@@ -7,7 +7,7 @@ import uncore.coherence.CoherencePolicy
 import uncore.constants._
 import util._
 import scala.math.max
-import cde.{Parameters, Field}
+import config._
 
 case object CacheBlockOffsetBits extends Field[Int]
 case object AmoAluOperandBits extends Field[Int]

src/main/scala/uncore/tilelink/Drivers.scala

@@ -5,7 +5,7 @@ import junctions._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
   val io = new Bundle {

src/main/scala/uncore/tilelink/Interconnect.scala

@@ -4,7 +4,7 @@ import Chisel._
 import junctions._
 import scala.collection.mutable.ArraySeq
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 
 /** PortedTileLinkNetworks combine a TileLink protocol with a particular physical

src/main/scala/uncore/tilelink/Network.scala

@@ -4,7 +4,7 @@ package uncore.tilelink
 
 import Chisel._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 case object LNEndpoints extends Field[Int]
 case object LNHeaderBits extends Field[Int]

src/main/scala/uncore/tilelink2/Legacy.scala

@@ -4,7 +4,7 @@ package uncore.tilelink2
 
 import Chisel._
 import diplomacy._
-import cde.Parameters
+import config._
 import uncore.tilelink._
 import uncore.constants._
 

src/main/scala/uncore/util/AmoAlu.scala

@@ -4,7 +4,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 import uncore.constants._
 
 class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {

src/main/scala/uncore/util/Counters.scala

@@ -3,7 +3,7 @@ package uncore.util
 import Chisel._
 import uncore.tilelink._
 import util.TwoWayCounter
-import cde.Parameters
+import config._
 
 class BeatCounterStatus extends Bundle {
   val idx = UInt()

src/main/scala/uncore/util/Enqueuer.scala

@@ -2,7 +2,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 /** Struct for describing per-channel queue depths */
 case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)

src/main/scala/unittest/Configs.scala

@@ -3,7 +3,7 @@
 package unittest
 
 import Chisel._
-import cde.{Parameters, Config, CDEMatchError}
+import config._
 import rocketchip.{BaseConfig, BasePlatformConfig}
 
 class WithJunctionsUnitTests extends Config(

src/main/scala/unittest/TestHarness.scala

@@ -3,7 +3,7 @@
 package unittest
 
 import Chisel._
-import cde._
+import config._
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = new Bundle { val success = Bool(OUTPUT) }

src/main/scala/unittest/UnitTest.scala

@@ -1,7 +1,7 @@
 package unittest
 
 import Chisel._
-import cde.{Field, Parameters}
+import config._
 import util.SimpleTimer
 
 trait HasUnitTestIO {

src/main/scala/util/Arbiters.scala

@@ -1,6 +1,6 @@
 package util
 import Chisel._
-import cde.Parameters
+import config._
 
 /** A generalized locking RR arbiter that addresses the limitations of the
  *  version in the Chisel standard library */

src/main/scala/util/BlackBoxRegs.scala

@@ -2,7 +2,7 @@ package util
 
 import Chisel._
 
-import cde.{Parameters}
+import config._
 
 /** This black-boxes an Async Reset
   *  (or Set)

src/main/scala/util/Counters.scala

@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 import scala.math.max
 
 // Produces 0-width value when counting to 1

src/main/scala/util/GeneratorUtils.scala

@@ -3,7 +3,7 @@
 package util
 
 import Chisel._
-import cde._
+import config._
 import diplomacy.LazyModule
 import java.io.{File, FileWriter}
 
@@ -24,7 +24,7 @@ case class ParsedInputNames(
   */
 trait HasGeneratorUtilities {
   def getConfig(names: ParsedInputNames): Config = {
-    names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
+    new Config(names.fullConfigClasses.foldRight(Parameters.empty) { case (currentName, config) =>
       val currentConfig = try {
         Class.forName(currentName).newInstance.asInstanceOf[Config]
       } catch {
@@ -32,7 +32,7 @@ trait HasGeneratorUtilities {
           throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
       }
       currentConfig ++ config
-    }
+    })
   }
 
   def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))

src/main/scala/util/HellaQueue.scala

@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
   val io = new QueueIO(data, entries)

src/main/scala/util/Misc.scala

@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 import scala.math._
 
 class ParameterizedBundle(implicit p: Parameters) extends Bundle {

src/main/scala/util/ReorderQueue.scala

@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
   val data = dType.cloneType