83 lines
2.2 KiB
Scala
83 lines
2.2 KiB
Scala
package junctions
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import Chisel._
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import config._
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class PociIO(implicit p: Parameters) extends HastiBundle()(p)
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{
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val paddr = UInt(OUTPUT, hastiAddrBits)
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val pwrite = Bool(OUTPUT)
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val psel = Bool(OUTPUT)
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val penable = Bool(OUTPUT)
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val pwdata = UInt(OUTPUT, hastiDataBits)
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val prdata = UInt(INPUT, hastiDataBits)
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val pready = Bool(INPUT)
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val pslverr = Bool(INPUT)
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}
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class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = new HastiSlaveIO
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val out = new PociIO
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}
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val s_idle :: s_setup :: s_access :: Nil = Enum(UInt(), 3)
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val state = Reg(init = s_idle)
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val transfer = io.in.hsel & io.in.htrans(1)
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switch (state) {
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is (s_idle) {
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when (transfer) { state := s_setup }
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}
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is (s_setup) {
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state := s_access
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}
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is (s_access) {
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when (io.out.pready & ~transfer) { state := s_idle }
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when (io.out.pready & transfer) { state := s_setup }
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when (~io.out.pready) { state := s_access }
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}
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}
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val haddr_reg = Reg(UInt(width = hastiAddrBits))
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val hwrite_reg = Reg(UInt(width = 1))
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when (transfer) {
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haddr_reg := io.in.haddr
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hwrite_reg := io.in.hwrite
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}
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io.out.paddr := haddr_reg
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io.out.pwrite := hwrite_reg(0)
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io.out.psel := (state =/= s_idle)
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io.out.penable := (state === s_access)
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io.out.pwdata := io.in.hwdata
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io.in.hrdata := io.out.prdata
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io.in.hready := ((state === s_access) & io.out.pready) | (state === s_idle)
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io.in.hresp := io.out.pslverr
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}
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class PociBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p)
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{
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val io = new Bundle {
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val master = new PociIO().flip
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val slaves = Vec(amap.size, new PociIO)
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}
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val psels = PriorityEncoderOH(
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(io.slaves zip amap) map { case (s, afn) => {
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s.paddr := io.master.paddr
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s.pwrite := io.master.pwrite
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s.pwdata := io.master.pwdata
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afn(io.master.paddr) && io.master.psel
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}})
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(io.slaves zip psels) foreach { case (s, psel) => {
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s.psel := psel
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s.penable := io.master.penable && psel
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} }
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io.master.prdata := Mux1H(psels, io.slaves.map(_.prdata))
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io.master.pready := Mux1H(psels, io.slaves.map(_.pready))
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io.master.pslverr := Mux1H(psels, io.slaves.map(_.pslverr))
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}
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