From 37a3c22639819ebb44b1115ead44f57f911b30cc Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 18 Nov 2016 14:05:14 -0800
Subject: [PATCH] rocketchip: move from using cde to config

---
 src/main/scala/coreplex/BaseCoreplex.scala         | 2 +-
 src/main/scala/coreplex/Configs.scala              | 2 +-
 src/main/scala/coreplex/Coreplex.scala             | 2 +-
 src/main/scala/coreplex/RISCVPlatform.scala        | 2 +-
 src/main/scala/coreplex/RocketPlex.scala           | 2 +-
 src/main/scala/groundtest/BusMasterTest.scala      | 2 +-
 src/main/scala/groundtest/CacheFillTest.scala      | 2 +-
 src/main/scala/groundtest/Comparator.scala         | 2 +-
 src/main/scala/groundtest/Configs.scala            | 2 +-
 src/main/scala/groundtest/Coreplex.scala           | 2 +-
 src/main/scala/groundtest/Regression.scala         | 2 +-
 src/main/scala/groundtest/TestHarness.scala        | 2 +-
 src/main/scala/groundtest/Tile.scala               | 2 +-
 src/main/scala/groundtest/Top.scala                | 2 +-
 src/main/scala/groundtest/TraceGen.scala           | 2 +-
 src/main/scala/groundtest/TrafficGenerator.scala   | 2 +-
 src/main/scala/junctions/NastiDriver.scala         | 2 +-
 src/main/scala/junctions/addrmap.scala             | 2 +-
 src/main/scala/junctions/hasti.scala               | 2 +-
 src/main/scala/junctions/jtag.scala                | 2 +-
 src/main/scala/junctions/nasti.scala               | 2 +-
 src/main/scala/junctions/poci.scala                | 2 +-
 src/main/scala/junctions/stream.scala              | 2 +-
 src/main/scala/rocket/arbiter.scala                | 2 +-
 src/main/scala/rocket/breakpoint.scala             | 2 +-
 src/main/scala/rocket/btb.scala                    | 2 +-
 src/main/scala/rocket/csr.scala                    | 2 +-
 src/main/scala/rocket/dcache.scala                 | 2 +-
 src/main/scala/rocket/dpath_alu.scala              | 2 +-
 src/main/scala/rocket/fpu.scala                    | 2 +-
 src/main/scala/rocket/frontend.scala               | 2 +-
 src/main/scala/rocket/ibuf.scala                   | 2 +-
 src/main/scala/rocket/icache.scala                 | 2 +-
 src/main/scala/rocket/idecode.scala                | 2 +-
 src/main/scala/rocket/nbdcache.scala               | 2 +-
 src/main/scala/rocket/ptw.scala                    | 2 +-
 src/main/scala/rocket/rocc.scala                   | 2 +-
 src/main/scala/rocket/rocket.scala                 | 2 +-
 src/main/scala/rocket/rvc.scala                    | 2 +-
 src/main/scala/rocket/tile.scala                   | 2 +-
 src/main/scala/rocket/tlb.scala                    | 2 +-
 src/main/scala/rocketchip/BaseTop.scala            | 2 +-
 src/main/scala/rocketchip/Configs.scala            | 2 +-
 src/main/scala/rocketchip/DebugTransport.scala     | 2 +-
 src/main/scala/rocketchip/ExampleTop.scala         | 2 +-
 src/main/scala/rocketchip/Periphery.scala          | 2 +-
 src/main/scala/rocketchip/RISCVPlatform.scala      | 2 +-
 src/main/scala/rocketchip/TestHarness.scala        | 2 +-
 src/main/scala/rocketchip/Utils.scala              | 2 +-
 src/main/scala/uncore/Builder.scala                | 2 +-
 src/main/scala/uncore/agents/Agents.scala          | 2 +-
 src/main/scala/uncore/agents/Broadcast.scala       | 2 +-
 src/main/scala/uncore/agents/Bufferless.scala      | 2 +-
 src/main/scala/uncore/agents/Cache.scala           | 2 +-
 src/main/scala/uncore/agents/Mmio.scala            | 2 +-
 src/main/scala/uncore/agents/StatelessBridge.scala | 2 +-
 src/main/scala/uncore/agents/StoreDataQueue.scala  | 2 +-
 src/main/scala/uncore/agents/Trackers.scala        | 2 +-
 src/main/scala/uncore/coherence/Metadata.scala     | 2 +-
 src/main/scala/uncore/converters/Ahb.scala         | 2 +-
 src/main/scala/uncore/converters/Nasti.scala       | 2 +-
 src/main/scala/uncore/converters/Tilelink.scala    | 2 +-
 src/main/scala/uncore/devices/Bram.scala           | 2 +-
 src/main/scala/uncore/devices/Debug.scala          | 2 +-
 src/main/scala/uncore/devices/Plic.scala           | 2 +-
 src/main/scala/uncore/devices/Prci.scala           | 2 +-
 src/main/scala/uncore/devices/Rom.scala            | 2 +-
 src/main/scala/uncore/tilelink/Arbiters.scala      | 2 +-
 src/main/scala/uncore/tilelink/Definitions.scala   | 2 +-
 src/main/scala/uncore/tilelink/Drivers.scala       | 2 +-
 src/main/scala/uncore/tilelink/Interconnect.scala  | 2 +-
 src/main/scala/uncore/tilelink/Network.scala       | 2 +-
 src/main/scala/uncore/tilelink2/Legacy.scala       | 2 +-
 src/main/scala/uncore/util/AmoAlu.scala            | 2 +-
 src/main/scala/uncore/util/Counters.scala          | 2 +-
 src/main/scala/uncore/util/Enqueuer.scala          | 2 +-
 src/main/scala/unittest/Configs.scala              | 2 +-
 src/main/scala/unittest/TestHarness.scala          | 2 +-
 src/main/scala/unittest/UnitTest.scala             | 2 +-
 src/main/scala/util/Arbiters.scala                 | 2 +-
 src/main/scala/util/BlackBoxRegs.scala             | 2 +-
 src/main/scala/util/Counters.scala                 | 2 +-
 src/main/scala/util/GeneratorUtils.scala           | 6 +++---
 src/main/scala/util/HellaQueue.scala               | 2 +-
 src/main/scala/util/Misc.scala                     | 2 +-
 src/main/scala/util/ReorderQueue.scala             | 2 +-
 86 files changed, 88 insertions(+), 88 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 88aae737..7123c50e 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 0584a681..4cffa127 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -15,7 +15,7 @@ import rocket._
 import util._
 import util.ConfigUtils._
 import rocketchip.{GlobalAddrMap}
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 
 class BaseCoreplexConfig extends Config (
   { (pname,site,here) =>
diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index a557dadf..ec258dc1 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._
diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala
index 952de6a0..18fb9368 100644
--- a/src/main/scala/coreplex/RISCVPlatform.scala
+++ b/src/main/scala/coreplex/RISCVPlatform.scala
@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._
diff --git a/src/main/scala/coreplex/RocketPlex.scala b/src/main/scala/coreplex/RocketPlex.scala
index 1477754b..6b9cc4d4 100644
--- a/src/main/scala/coreplex/RocketPlex.scala
+++ b/src/main/scala/coreplex/RocketPlex.scala
@@ -1,7 +1,7 @@
 package coreplex
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import diplomacy._
 import uncore.tilelink2._
 import uncore.coherence._
diff --git a/src/main/scala/groundtest/BusMasterTest.scala b/src/main/scala/groundtest/BusMasterTest.scala
index b9859c74..ad12c808 100644
--- a/src/main/scala/groundtest/BusMasterTest.scala
+++ b/src/main/scala/groundtest/BusMasterTest.scala
@@ -7,7 +7,7 @@ import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
 import junctions.HasAddrMapParameters
 import rocketchip._
-import cde.Parameters
+import config._
 
 /**
  * An example bus mastering devices that writes some preset data to memory.
diff --git a/src/main/scala/groundtest/CacheFillTest.scala b/src/main/scala/groundtest/CacheFillTest.scala
index f97ce852..685bc8bc 100644
--- a/src/main/scala/groundtest/CacheFillTest.scala
+++ b/src/main/scala/groundtest/CacheFillTest.scala
@@ -5,7 +5,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
     with HasTileLinkParameters {
diff --git a/src/main/scala/groundtest/Comparator.scala b/src/main/scala/groundtest/Comparator.scala
index 27f4ce3f..7324c6e6 100644
--- a/src/main/scala/groundtest/Comparator.scala
+++ b/src/main/scala/groundtest/Comparator.scala
@@ -7,7 +7,7 @@ import junctions._
 import rocket._
 import util.Timer
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 case class ComparatorParameters(
   targets:    Seq[Long], 
diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala
index f2da1d23..e08a6976 100644
--- a/src/main/scala/groundtest/Configs.scala
+++ b/src/main/scala/groundtest/Configs.scala
@@ -8,7 +8,7 @@ import uncore.coherence._
 import uncore.agents._
 import uncore.devices.NTiles
 import junctions._
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 import scala.math.max
 import coreplex._
 import rocketchip._
diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala
index fd94eb17..23529037 100644
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@@ -1,7 +1,7 @@
 package groundtest
 
 import Chisel._
-import cde.Parameters
+import config._
 import diplomacy._
 import coreplex._
 import uncore.devices.NTiles
diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala
index d14d5032..20a3d2bd 100644
--- a/src/main/scala/groundtest/Regression.scala
+++ b/src/main/scala/groundtest/Regression.scala
@@ -8,7 +8,7 @@ import util._
 import junctions.HasAddrMapParameters
 import rocket._
 import rocketchip._
-import cde.{Parameters, Field}
+import config._
 
 class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
   val start = Bool(INPUT)
diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala
index a05d0ae1..fd265858 100644
--- a/src/main/scala/groundtest/TestHarness.scala
+++ b/src/main/scala/groundtest/TestHarness.scala
@@ -2,7 +2,7 @@ package groundtest
 
 import Chisel._
 import diplomacy._
-import cde.Parameters
+import config._
 import rocketchip._
 import util._
 
diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
index 387fa9ac..3a6e2cff 100644
--- a/src/main/scala/groundtest/Tile.scala
+++ b/src/main/scala/groundtest/Tile.scala
@@ -11,7 +11,7 @@ import scala.util.Random
 import scala.collection.mutable.ListBuffer
 import junctions.HasAddrMapParameters
 import util.ParameterizedBundle
-import cde.{Parameters, Field}
+import config._
 
 case object BuildGroundTest extends Field[Parameters => GroundTest]
 
diff --git a/src/main/scala/groundtest/Top.scala b/src/main/scala/groundtest/Top.scala
index 30d2c781..613bb39a 100644
--- a/src/main/scala/groundtest/Top.scala
+++ b/src/main/scala/groundtest/Top.scala
@@ -1,7 +1,7 @@
 package groundtest
 
 import Chisel._
-import cde.Parameters
+import config._
 import diplomacy._
 import coreplex._
 import rocketchip._
diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
index 97ec6682..3a514e3e 100644
--- a/src/main/scala/groundtest/TraceGen.scala
+++ b/src/main/scala/groundtest/TraceGen.scala
@@ -24,7 +24,7 @@ import junctions._
 import rocket._
 import util.{Timer, DynamicTimer}
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 // =======
 // Outline
diff --git a/src/main/scala/groundtest/TrafficGenerator.scala b/src/main/scala/groundtest/TrafficGenerator.scala
index af2aeb50..fd1f7194 100644
--- a/src/main/scala/groundtest/TrafficGenerator.scala
+++ b/src/main/scala/groundtest/TrafficGenerator.scala
@@ -8,7 +8,7 @@ import junctions._
 import rocket._
 import util.SimpleTimer
 import scala.util.Random
-import cde.{Parameters, Field}
+import config._
 
 case class TrafficGeneratorParameters(
   maxRequests: Int,
diff --git a/src/main/scala/junctions/NastiDriver.scala b/src/main/scala/junctions/NastiDriver.scala
index 685743d2..f7de9da4 100644
--- a/src/main/scala/junctions/NastiDriver.scala
+++ b/src/main/scala/junctions/NastiDriver.scala
@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
     (implicit p: Parameters) extends NastiModule {
diff --git a/src/main/scala/junctions/addrmap.scala b/src/main/scala/junctions/addrmap.scala
index 86fdd276..a94ea32d 100644
--- a/src/main/scala/junctions/addrmap.scala
+++ b/src/main/scala/junctions/addrmap.scala
@@ -3,7 +3,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import scala.collection.mutable.HashMap
 
 case object PAddrBits extends Field[Int]
diff --git a/src/main/scala/junctions/hasti.scala b/src/main/scala/junctions/hasti.scala
index 9a36048f..d9c08d43 100644
--- a/src/main/scala/junctions/hasti.scala
+++ b/src/main/scala/junctions/hasti.scala
@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import unittest.UnitTest
 import util.ParameterizedBundle
 
diff --git a/src/main/scala/junctions/jtag.scala b/src/main/scala/junctions/jtag.scala
index a9613637..485ab4da 100644
--- a/src/main/scala/junctions/jtag.scala
+++ b/src/main/scala/junctions/jtag.scala
@@ -1,6 +1,6 @@
 package junctions
 import Chisel._
-import cde.{Parameters}
+import config._
 
 class JTAGIO(drvTdo: Boolean = false) extends Bundle {
   val TCK = Clock(OUTPUT)
diff --git a/src/main/scala/junctions/nasti.scala b/src/main/scala/junctions/nasti.scala
index cab7ecd0..acc9e21f 100644
--- a/src/main/scala/junctions/nasti.scala
+++ b/src/main/scala/junctions/nasti.scala
@@ -5,7 +5,7 @@ import Chisel._
 import scala.math.max
 import scala.collection.mutable.ArraySeq
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case object NastiKey extends Field[NastiParameters]
 
diff --git a/src/main/scala/junctions/poci.scala b/src/main/scala/junctions/poci.scala
index ac089164..7fd40205 100644
--- a/src/main/scala/junctions/poci.scala
+++ b/src/main/scala/junctions/poci.scala
@@ -1,7 +1,7 @@
 package junctions
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 
 class PociIO(implicit p: Parameters) extends HastiBundle()(p)
 {
diff --git a/src/main/scala/junctions/stream.scala b/src/main/scala/junctions/stream.scala
index 24f9ad58..c71dfd8d 100644
--- a/src/main/scala/junctions/stream.scala
+++ b/src/main/scala/junctions/stream.scala
@@ -2,7 +2,7 @@ package junctions
 
 import Chisel._
 import NastiConstants._
-import cde.Parameters
+import config._
 
 class StreamChannel(w: Int) extends Bundle {
   val data = UInt(width = w)
diff --git a/src/main/scala/rocket/arbiter.scala b/src/main/scala/rocket/arbiter.scala
index de43dd6d..6a481287 100644
--- a/src/main/scala/rocket/arbiter.scala
+++ b/src/main/scala/rocket/arbiter.scala
@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util.{ParameterizedBundle, DecoupledHelper}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
diff --git a/src/main/scala/rocket/breakpoint.scala b/src/main/scala/rocket/breakpoint.scala
index 36767e70..e91db306 100644
--- a/src/main/scala/rocket/breakpoint.scala
+++ b/src/main/scala/rocket/breakpoint.scala
@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.Parameters
+import config._
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
   val ttype = UInt(width = 4)
diff --git a/src/main/scala/rocket/btb.scala b/src/main/scala/rocket/btb.scala
index 3bf9e351..98d06f04 100644
--- a/src/main/scala/rocket/btb.scala
+++ b/src/main/scala/rocket/btb.scala
@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util._
 import Chisel.ImplicitConversions._
 import uncore.agents.PseudoLRU
diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala
index c25cd682..4c67d2c2 100644
--- a/src/main/scala/rocket/csr.scala
+++ b/src/main/scala/rocket/csr.scala
@@ -4,7 +4,7 @@ package rocket
 
 import Chisel._
 import Instructions._
-import cde.{Parameters, Field}
+import config._
 import uncore.devices._
 import util._
 import Chisel.ImplicitConversions._
diff --git a/src/main/scala/rocket/dcache.scala b/src/main/scala/rocket/dcache.scala
index 0665e384..14991eda 100644
--- a/src/main/scala/rocket/dcache.scala
+++ b/src/main/scala/rocket/dcache.scala
@@ -12,7 +12,7 @@ import uncore.util._
 import util._
 import TLMessages._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
   val addr = Bits(width = untagBits)
diff --git a/src/main/scala/rocket/dpath_alu.scala b/src/main/scala/rocket/dpath_alu.scala
index 0f9480cb..90554656 100644
--- a/src/main/scala/rocket/dpath_alu.scala
+++ b/src/main/scala/rocket/dpath_alu.scala
@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import Instructions._
 
 object ALU
diff --git a/src/main/scala/rocket/fpu.scala b/src/main/scala/rocket/fpu.scala
index b825d1a9..691354d5 100644
--- a/src/main/scala/rocket/fpu.scala
+++ b/src/main/scala/rocket/fpu.scala
@@ -8,7 +8,7 @@ import util._
 import Chisel.ImplicitConversions._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
-import cde.{Parameters, Field}
+import config._
 
 case class FPUConfig(
   divSqrt: Boolean = true,
diff --git a/src/main/scala/rocket/frontend.scala b/src/main/scala/rocket/frontend.scala
index cb22bd48..8ffd43ed 100644
--- a/src/main/scala/rocket/frontend.scala
+++ b/src/main/scala/rocket/frontend.scala
@@ -4,7 +4,7 @@ import Chisel._
 import uncore.tilelink._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)
diff --git a/src/main/scala/rocket/ibuf.scala b/src/main/scala/rocket/ibuf.scala
index 9ae99883..3f076008 100644
--- a/src/main/scala/rocket/ibuf.scala
+++ b/src/main/scala/rocket/ibuf.scala
@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
   val pf0 = Bool() // page fault on first half of instruction
diff --git a/src/main/scala/rocket/icache.scala b/src/main/scala/rocket/icache.scala
index ef90453e..bbff1cc0 100644
--- a/src/main/scala/rocket/icache.scala
+++ b/src/main/scala/rocket/icache.scala
@@ -6,7 +6,7 @@ import uncore.tilelink._
 import uncore.util._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats
diff --git a/src/main/scala/rocket/idecode.scala b/src/main/scala/rocket/idecode.scala
index 30fa7a8d..018e723c 100644
--- a/src/main/scala/rocket/idecode.scala
+++ b/src/main/scala/rocket/idecode.scala
@@ -6,7 +6,7 @@ import Chisel._
 import Instructions._
 import uncore.constants.MemoryOpConstants._
 import ALU._
-import cde.Parameters
+import config._
 import util._
 import Chisel.ImplicitConversions._
 
diff --git a/src/main/scala/rocket/nbdcache.scala b/src/main/scala/rocket/nbdcache.scala
index 7d6f12fe..8775a6a0 100644
--- a/src/main/scala/rocket/nbdcache.scala
+++ b/src/main/scala/rocket/nbdcache.scala
@@ -11,7 +11,7 @@ import uncore.util._
 import diplomacy._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case class DCacheConfig(
   nMSHRs: Int = 1,
diff --git a/src/main/scala/rocket/ptw.scala b/src/main/scala/rocket/ptw.scala
index 31da1358..60e8fa92 100644
--- a/src/main/scala/rocket/ptw.scala
+++ b/src/main/scala/rocket/ptw.scala
@@ -7,7 +7,7 @@ import uncore.agents._
 import uncore.constants._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val prv = Bits(width = 2)
diff --git a/src/main/scala/rocket/rocc.scala b/src/main/scala/rocket/rocc.scala
index 64dbdec2..4503c984 100644
--- a/src/main/scala/rocket/rocc.scala
+++ b/src/main/scala/rocket/rocc.scala
@@ -8,7 +8,7 @@ import uncore.constants._
 import uncore.agents.CacheName
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]
diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala
index 85d31dcb..ea350c84 100644
--- a/src/main/scala/rocket/rocket.scala
+++ b/src/main/scala/rocket/rocket.scala
@@ -9,7 +9,7 @@ import uncore.constants._
 import junctions.HasAddrMapParameters
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object XLen extends Field[Int]
 case object FetchWidth extends Field[Int]
diff --git a/src/main/scala/rocket/rvc.scala b/src/main/scala/rocket/rvc.scala
index e7ae1fae..d7529f9d 100644
--- a/src/main/scala/rocket/rvc.scala
+++ b/src/main/scala/rocket/rvc.scala
@@ -3,7 +3,7 @@ package rocket
 import Chisel._
 import Chisel.ImplicitConversions._
 import util._
-import cde.Parameters
+import config._
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(width = 32)
diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala
index 0bdaf20e..1ebc8836 100644
--- a/src/main/scala/rocket/tile.scala
+++ b/src/main/scala/rocket/tile.scala
@@ -10,7 +10,7 @@ import uncore.agents._
 import uncore.converters._
 import uncore.devices._
 import util._
-import cde.{Parameters, Field}
+import config._
 import scala.collection.mutable.ListBuffer
 
 case object BuildRoCC extends Field[Seq[RoccParameters]]
diff --git a/src/main/scala/rocket/tlb.scala b/src/main/scala/rocket/tlb.scala
index 5f137583..339f2e84 100644
--- a/src/main/scala/rocket/tlb.scala
+++ b/src/main/scala/rocket/tlb.scala
@@ -7,7 +7,7 @@ import util._
 import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
-import cde.{Parameters, Field}
+import config._
 import uncore.agents._
 import uncore.coherence._
 
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index d2c066b1..a5f100ab 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import uncore.tilelink._
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index f5889c47..b98af3db 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -16,7 +16,7 @@ import scala.math.max
 import scala.collection.mutable.{LinkedHashSet, ListBuffer}
 import scala.collection.immutable.HashMap
 import DefaultTestSuites._
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import config._
 
 class BasePlatformConfig extends Config(
   (pname,site,here) => pname match {
diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala
index 9a58e58f..1d4949a3 100644
--- a/src/main/scala/rocketchip/DebugTransport.scala
+++ b/src/main/scala/rocketchip/DebugTransport.scala
@@ -4,7 +4,7 @@ import Chisel._
 import uncore.devices._
 import junctions._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case object IncludeJtagDTM extends Field[Boolean]
 
diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala
index 4b8efbc7..a8ff4adf 100644
--- a/src/main/scala/rocketchip/ExampleTop.scala
+++ b/src/main/scala/rocketchip/ExampleTop.scala
@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import coreplex._
 import rocketchip._
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 681c7f66..aaf6fd4f 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field, Dump}
+import config._
 import junctions._
 import junctions.NastiConstants._
 import diplomacy._
diff --git a/src/main/scala/rocketchip/RISCVPlatform.scala b/src/main/scala/rocketchip/RISCVPlatform.scala
index d3d7f34d..29c930c3 100644
--- a/src/main/scala/rocketchip/RISCVPlatform.scala
+++ b/src/main/scala/rocketchip/RISCVPlatform.scala
@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field, Dump}
+import config._
 import diplomacy._
 import uncore.tilelink2._
 import uncore.devices._
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 363ed0f8..092a290b 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -3,7 +3,7 @@
 package rocketchip
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions._
 import diplomacy._
 import coreplex._
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index ed37bf98..329c352e 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -2,7 +2,7 @@
 
 package rocketchip
 
-import cde.{Parameters, Dump}
+import config._
 import junctions._
 import diplomacy._
 import uncore.devices._
diff --git a/src/main/scala/uncore/Builder.scala b/src/main/scala/uncore/Builder.scala
index 562315d9..e55cdaa4 100644
--- a/src/main/scala/uncore/Builder.scala
+++ b/src/main/scala/uncore/Builder.scala
@@ -1,7 +1,7 @@
 package uncore
 
 import Chisel._
-import cde.{Config, Parameters, ParameterDump, Knob, Dump, CDEMatchError}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.agents._
diff --git a/src/main/scala/uncore/agents/Agents.scala b/src/main/scala/uncore/agents/Agents.scala
index afed6636..0c3725a7 100644
--- a/src/main/scala/uncore/agents/Agents.scala
+++ b/src/main/scala/uncore/agents/Agents.scala
@@ -3,7 +3,7 @@
 package uncore.agents
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.converters._
diff --git a/src/main/scala/uncore/agents/Broadcast.scala b/src/main/scala/uncore/agents/Broadcast.scala
index 6226b83e..f8ba7d17 100644
--- a/src/main/scala/uncore/agents/Broadcast.scala
+++ b/src/main/scala/uncore/agents/Broadcast.scala
@@ -8,7 +8,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 class L2BroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
 
diff --git a/src/main/scala/uncore/agents/Bufferless.scala b/src/main/scala/uncore/agents/Bufferless.scala
index 5371d74a..985508d1 100644
--- a/src/main/scala/uncore/agents/Bufferless.scala
+++ b/src/main/scala/uncore/agents/Bufferless.scala
@@ -6,7 +6,7 @@ import Chisel._
 import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 
 
 class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
diff --git a/src/main/scala/uncore/agents/Cache.scala b/src/main/scala/uncore/agents/Cache.scala
index ac6267b7..6f79a945 100644
--- a/src/main/scala/uncore/agents/Cache.scala
+++ b/src/main/scala/uncore/agents/Cache.scala
@@ -12,7 +12,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case class CacheConfig(
   nSets:         Int,
diff --git a/src/main/scala/uncore/agents/Mmio.scala b/src/main/scala/uncore/agents/Mmio.scala
index 08ccc4d3..39ee70cd 100644
--- a/src/main/scala/uncore/agents/Mmio.scala
+++ b/src/main/scala/uncore/agents/Mmio.scala
@@ -2,7 +2,7 @@ package uncore.agents
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 class MMIOTileLinkManagerData(implicit p: Parameters)
     extends TLBundle()(p)
diff --git a/src/main/scala/uncore/agents/StatelessBridge.scala b/src/main/scala/uncore/agents/StatelessBridge.scala
index 0ed818cf..02edacf0 100644
--- a/src/main/scala/uncore/agents/StatelessBridge.scala
+++ b/src/main/scala/uncore/agents/StatelessBridge.scala
@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.devices._
-import cde.{Parameters, Field, Config}
+import config._
 
 /** The ManagerToClientStateless Bridge does not maintain any state for the messages
   *  which pass through it. It simply passes the messages back and forth without any
diff --git a/src/main/scala/uncore/agents/StoreDataQueue.scala b/src/main/scala/uncore/agents/StoreDataQueue.scala
index 041d04db..71aee4ed 100644
--- a/src/main/scala/uncore/agents/StoreDataQueue.scala
+++ b/src/main/scala/uncore/agents/StoreDataQueue.scala
@@ -3,7 +3,7 @@
 package uncore.agents
 import Chisel._
 import uncore.tilelink._
-import cde.{Parameters, Field}
+import config._
 
 case object L2StoreDataQueueDepth extends Field[Int]
 
diff --git a/src/main/scala/uncore/agents/Trackers.scala b/src/main/scala/uncore/agents/Trackers.scala
index a63735ac..7813a445 100644
--- a/src/main/scala/uncore/agents/Trackers.scala
+++ b/src/main/scala/uncore/agents/Trackers.scala
@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.util._
 import util._
-import cde.{Field, Parameters}
+import config._
 import scala.math.max
 
 case object EnableL2Logging extends Field[Boolean]
diff --git a/src/main/scala/uncore/coherence/Metadata.scala b/src/main/scala/uncore/coherence/Metadata.scala
index c0d7a6bf..34fae81a 100644
--- a/src/main/scala/uncore/coherence/Metadata.scala
+++ b/src/main/scala/uncore/coherence/Metadata.scala
@@ -5,7 +5,7 @@ package uncore.coherence
 import Chisel._
 import uncore.tilelink._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 
 /** Identifies the TLId of the inner network in a hierarchical cache controller */ 
 case object InnerTLId extends Field[String]
diff --git a/src/main/scala/uncore/converters/Ahb.scala b/src/main/scala/uncore/converters/Ahb.scala
index c298e7b3..d9457065 100644
--- a/src/main/scala/uncore/converters/Ahb.scala
+++ b/src/main/scala/uncore/converters/Ahb.scala
@@ -5,7 +5,7 @@ import junctions._
 import uncore.tilelink._
 import uncore.util._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 import HastiConstants._
 
 /* We need to translate TileLink requests into operations we can actually execute on AHB.
diff --git a/src/main/scala/uncore/converters/Nasti.scala b/src/main/scala/uncore/converters/Nasti.scala
index 3477e976..8ff46afb 100644
--- a/src/main/scala/uncore/converters/Nasti.scala
+++ b/src/main/scala/uncore/converters/Nasti.scala
@@ -6,7 +6,7 @@ import util.{ReorderQueue, DecoupledHelper}
 import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class IdMapper(val inIdBits: Int, val outIdBits: Int,
diff --git a/src/main/scala/uncore/converters/Tilelink.scala b/src/main/scala/uncore/converters/Tilelink.scala
index 94cc768f..7d6c3f13 100644
--- a/src/main/scala/uncore/converters/Tilelink.scala
+++ b/src/main/scala/uncore/converters/Tilelink.scala
@@ -8,7 +8,7 @@ import uncore.util._
 import uncore.constants._
 import uncore.devices.TileLinkTestRAM
 import unittest.UnitTest
-import cde.Parameters
+import config._
 
 /** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
 object TileLinkIOWrapper {
diff --git a/src/main/scala/uncore/devices/Bram.scala b/src/main/scala/uncore/devices/Bram.scala
index 447dccfe..e7d6751d 100644
--- a/src/main/scala/uncore/devices/Bram.scala
+++ b/src/main/scala/uncore/devices/Bram.scala
@@ -1,7 +1,7 @@
 package uncore.devices
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import unittest.UnitTest
 import junctions._
 import uncore.tilelink._
diff --git a/src/main/scala/uncore/devices/Debug.scala b/src/main/scala/uncore/devices/Debug.scala
index ea2662e2..cf3010e3 100644
--- a/src/main/scala/uncore/devices/Debug.scala
+++ b/src/main/scala/uncore/devices/Debug.scala
@@ -7,7 +7,7 @@ import junctions._
 import util._
 import regmapper._
 import uncore.tilelink2._
-import cde.{Parameters, Config, Field}
+import config._
 
 // *****************************************
 // Constants which are interesting even
diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala
index 830cd88a..f49782a0 100644
--- a/src/main/scala/uncore/devices/Plic.scala
+++ b/src/main/scala/uncore/devices/Plic.scala
@@ -9,7 +9,7 @@ import junctions._
 import diplomacy._
 import regmapper._
 import uncore.tilelink2._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class GatewayPLICIO extends Bundle {
diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala
index 604c89ab..ef73294c 100644
--- a/src/main/scala/uncore/devices/Prci.scala
+++ b/src/main/scala/uncore/devices/Prci.scala
@@ -11,7 +11,7 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 import scala.math.{min,max}
-import cde.{Parameters, Field}
+import config._
 
 /** Number of tiles */
 case object NTiles extends Field[Int]
diff --git a/src/main/scala/uncore/devices/Rom.scala b/src/main/scala/uncore/devices/Rom.scala
index c47f2ab1..f46ce22e 100644
--- a/src/main/scala/uncore/devices/Rom.scala
+++ b/src/main/scala/uncore/devices/Rom.scala
@@ -7,7 +7,7 @@ import diplomacy._
 import uncore.tilelink._
 import uncore.tilelink2._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {
diff --git a/src/main/scala/uncore/tilelink/Arbiters.scala b/src/main/scala/uncore/tilelink/Arbiters.scala
index 3b76b88f..c81ccee8 100644
--- a/src/main/scala/uncore/tilelink/Arbiters.scala
+++ b/src/main/scala/uncore/tilelink/Arbiters.scala
@@ -1,7 +1,7 @@
 package uncore.tilelink
 import Chisel._
 import junctions._
-import cde.{Parameters, Field}
+import config._
 
 /** Utility functions for constructing TileLinkIO arbiters */
 trait TileLinkArbiterLike extends HasTileLinkParameters {
diff --git a/src/main/scala/uncore/tilelink/Definitions.scala b/src/main/scala/uncore/tilelink/Definitions.scala
index c1f12f90..88becdd4 100644
--- a/src/main/scala/uncore/tilelink/Definitions.scala
+++ b/src/main/scala/uncore/tilelink/Definitions.scala
@@ -7,7 +7,7 @@ import uncore.coherence.CoherencePolicy
 import uncore.constants._
 import util._
 import scala.math.max
-import cde.{Parameters, Field}
+import config._
 
 case object CacheBlockOffsetBits extends Field[Int]
 case object AmoAluOperandBits extends Field[Int]
diff --git a/src/main/scala/uncore/tilelink/Drivers.scala b/src/main/scala/uncore/tilelink/Drivers.scala
index 43d127a5..c926779a 100644
--- a/src/main/scala/uncore/tilelink/Drivers.scala
+++ b/src/main/scala/uncore/tilelink/Drivers.scala
@@ -5,7 +5,7 @@ import junctions._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
   val io = new Bundle {
diff --git a/src/main/scala/uncore/tilelink/Interconnect.scala b/src/main/scala/uncore/tilelink/Interconnect.scala
index 8a2de1b7..544a6c51 100644
--- a/src/main/scala/uncore/tilelink/Interconnect.scala
+++ b/src/main/scala/uncore/tilelink/Interconnect.scala
@@ -4,7 +4,7 @@ import Chisel._
 import junctions._
 import scala.collection.mutable.ArraySeq
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 
 /** PortedTileLinkNetworks combine a TileLink protocol with a particular physical
diff --git a/src/main/scala/uncore/tilelink/Network.scala b/src/main/scala/uncore/tilelink/Network.scala
index 2a5fd8ab..51702b32 100644
--- a/src/main/scala/uncore/tilelink/Network.scala
+++ b/src/main/scala/uncore/tilelink/Network.scala
@@ -4,7 +4,7 @@ package uncore.tilelink
 
 import Chisel._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 case object LNEndpoints extends Field[Int]
 case object LNHeaderBits extends Field[Int]
diff --git a/src/main/scala/uncore/tilelink2/Legacy.scala b/src/main/scala/uncore/tilelink2/Legacy.scala
index 98ae2ae2..2a8b0341 100644
--- a/src/main/scala/uncore/tilelink2/Legacy.scala
+++ b/src/main/scala/uncore/tilelink2/Legacy.scala
@@ -4,7 +4,7 @@ package uncore.tilelink2
 
 import Chisel._
 import diplomacy._
-import cde.Parameters
+import config._
 import uncore.tilelink._
 import uncore.constants._
 
diff --git a/src/main/scala/uncore/util/AmoAlu.scala b/src/main/scala/uncore/util/AmoAlu.scala
index 40ae8d72..ce80bab0 100644
--- a/src/main/scala/uncore/util/AmoAlu.scala
+++ b/src/main/scala/uncore/util/AmoAlu.scala
@@ -4,7 +4,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 import uncore.constants._
 
 class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
diff --git a/src/main/scala/uncore/util/Counters.scala b/src/main/scala/uncore/util/Counters.scala
index 52209797..2ad49f0b 100644
--- a/src/main/scala/uncore/util/Counters.scala
+++ b/src/main/scala/uncore/util/Counters.scala
@@ -3,7 +3,7 @@ package uncore.util
 import Chisel._
 import uncore.tilelink._
 import util.TwoWayCounter
-import cde.Parameters
+import config._
 
 class BeatCounterStatus extends Bundle {
   val idx = UInt()
diff --git a/src/main/scala/uncore/util/Enqueuer.scala b/src/main/scala/uncore/util/Enqueuer.scala
index 3018821d..163577dc 100644
--- a/src/main/scala/uncore/util/Enqueuer.scala
+++ b/src/main/scala/uncore/util/Enqueuer.scala
@@ -2,7 +2,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 /** Struct for describing per-channel queue depths */
 case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
index 39f4adf7..393f0cfe 100644
--- a/src/main/scala/unittest/Configs.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -3,7 +3,7 @@
 package unittest
 
 import Chisel._
-import cde.{Parameters, Config, CDEMatchError}
+import config._
 import rocketchip.{BaseConfig, BasePlatformConfig}
 
 class WithJunctionsUnitTests extends Config(
diff --git a/src/main/scala/unittest/TestHarness.scala b/src/main/scala/unittest/TestHarness.scala
index b5804646..1f979b74 100644
--- a/src/main/scala/unittest/TestHarness.scala
+++ b/src/main/scala/unittest/TestHarness.scala
@@ -3,7 +3,7 @@
 package unittest
 
 import Chisel._
-import cde._
+import config._
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = new Bundle { val success = Bool(OUTPUT) }
diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala
index 1103cf30..4dbc76e5 100644
--- a/src/main/scala/unittest/UnitTest.scala
+++ b/src/main/scala/unittest/UnitTest.scala
@@ -1,7 +1,7 @@
 package unittest
 
 import Chisel._
-import cde.{Field, Parameters}
+import config._
 import util.SimpleTimer
 
 trait HasUnitTestIO {
diff --git a/src/main/scala/util/Arbiters.scala b/src/main/scala/util/Arbiters.scala
index b5518720..b3421496 100644
--- a/src/main/scala/util/Arbiters.scala
+++ b/src/main/scala/util/Arbiters.scala
@@ -1,6 +1,6 @@
 package util
 import Chisel._
-import cde.Parameters
+import config._
 
 /** A generalized locking RR arbiter that addresses the limitations of the
  *  version in the Chisel standard library */
diff --git a/src/main/scala/util/BlackBoxRegs.scala b/src/main/scala/util/BlackBoxRegs.scala
index a03c3bfa..14bba000 100644
--- a/src/main/scala/util/BlackBoxRegs.scala
+++ b/src/main/scala/util/BlackBoxRegs.scala
@@ -2,7 +2,7 @@ package util
 
 import Chisel._
 
-import cde.{Parameters}
+import config._
 
 /** This black-boxes an Async Reset
   *  (or Set)
diff --git a/src/main/scala/util/Counters.scala b/src/main/scala/util/Counters.scala
index 2f27ccaf..0d9bccc1 100644
--- a/src/main/scala/util/Counters.scala
+++ b/src/main/scala/util/Counters.scala
@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 import scala.math.max
 
 // Produces 0-width value when counting to 1
diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala
index 1d76f07a..29161912 100644
--- a/src/main/scala/util/GeneratorUtils.scala
+++ b/src/main/scala/util/GeneratorUtils.scala
@@ -3,7 +3,7 @@
 package util
 
 import Chisel._
-import cde._
+import config._
 import diplomacy.LazyModule
 import java.io.{File, FileWriter}
 
@@ -24,7 +24,7 @@ case class ParsedInputNames(
   */
 trait HasGeneratorUtilities {
   def getConfig(names: ParsedInputNames): Config = {
-    names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
+    new Config(names.fullConfigClasses.foldRight(Parameters.empty) { case (currentName, config) =>
       val currentConfig = try {
         Class.forName(currentName).newInstance.asInstanceOf[Config]
       } catch {
@@ -32,7 +32,7 @@ trait HasGeneratorUtilities {
           throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
       }
       currentConfig ++ config
-    }
+    })
   }
 
   def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))
diff --git a/src/main/scala/util/HellaQueue.scala b/src/main/scala/util/HellaQueue.scala
index acaa800b..53a7e5f9 100644
--- a/src/main/scala/util/HellaQueue.scala
+++ b/src/main/scala/util/HellaQueue.scala
@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
   val io = new QueueIO(data, entries)
diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala
index c1eec648..f674160b 100644
--- a/src/main/scala/util/Misc.scala
+++ b/src/main/scala/util/Misc.scala
@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 import scala.math._
 
 class ParameterizedBundle(implicit p: Parameters) extends Bundle {
diff --git a/src/main/scala/util/ReorderQueue.scala b/src/main/scala/util/ReorderQueue.scala
index 458001af..c19115a0 100644
--- a/src/main/scala/util/ReorderQueue.scala
+++ b/src/main/scala/util/ReorderQueue.scala
@@ -1,7 +1,7 @@
 package util
 
 import Chisel._
-import cde.Parameters
+import config._
 
 class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
   val data = dType.cloneType