From 369ee74a2c821ca6941b41715e0973d947fbcff3 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 2 Dec 2015 16:28:23 -0800 Subject: [PATCH] change names of RoCC tilelink interfaces to be more sensible --- rocket/src/main/scala/rocc.scala | 30 ++++++++++++------------------ rocket/src/main/scala/tile.scala | 10 +++++----- 2 files changed, 17 insertions(+), 23 deletions(-) diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index 76673a6f..f2b2decd 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -42,8 +42,8 @@ class RoCCInterface(implicit p: Parameters) extends Bundle { val interrupt = Bool(OUTPUT) // These should be handled differently, eventually - val imem = new ClientUncachedTileLinkIO - val dmem = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO) + val autl = new ClientUncachedTileLinkIO + val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO) val iptw = new TLBPTWIO val dptw = new TLBPTWIO val pptw = new TLBPTWIO @@ -122,10 +122,8 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) { io.mem.req.bits.data := Bits(0) // we're not performing any stores... io.mem.invalidate_lr := false - io.imem.acquire.valid := false - io.imem.grant.ready := false - io.dmem.head.acquire.valid := false - io.dmem.head.grant.ready := false + io.autl.acquire.valid := false + io.autl.grant.ready := false io.iptw.req.valid := false io.dptw.req.valid := false io.pptw.req.valid := false @@ -172,10 +170,8 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) { io.busy := (state =/= s_idle) io.interrupt := Bool(false) io.mem.req.valid := Bool(false) - io.dmem.head.acquire.valid := Bool(false) - io.dmem.head.grant.ready := Bool(false) - io.imem.acquire.valid := Bool(false) - io.imem.grant.ready := Bool(false) + io.autl.acquire.valid := Bool(false) + io.autl.grant.ready := Bool(false) io.iptw.req.valid := Bool(false) io.pptw.req.valid := Bool(false) } @@ -197,7 +193,7 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p) val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5) val state = Reg(init = s_idle) - val gnt = io.dmem.head.grant.bits + val gnt = io.autl.grant.bits val recv_data = Reg(UInt(width = tlDataBits)) val recv_beat = Reg(UInt(width = tlBeatAddrBits)) @@ -218,9 +214,9 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p) io.resp.valid := (state === s_resp) io.resp.bits.rd := resp_rd io.resp.bits.data := count - io.dmem.head.acquire.valid := (state === s_acq) - io.dmem.head.acquire.bits := GetBlock(addr_block = addr_block) - io.dmem.head.grant.ready := (state === s_gnt) + io.autl.acquire.valid := (state === s_acq) + io.autl.acquire.bits := GetBlock(addr_block = addr_block) + io.autl.grant.ready := (state === s_gnt) when (io.cmd.fire()) { addr := io.cmd.bits.rs1 @@ -231,9 +227,9 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p) state := s_acq } - when (io.dmem.head.acquire.fire()) { state := s_gnt } + when (io.autl.acquire.fire()) { state := s_gnt } - when (io.dmem.head.grant.fire()) { + when (io.autl.grant.fire()) { recv_beat := gnt.addr_beat recv_data := gnt.data state := s_check @@ -257,8 +253,6 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p) io.busy := (state =/= s_idle) io.interrupt := Bool(false) io.mem.req.valid := Bool(false) - io.imem.acquire.valid := Bool(false) - io.imem.grant.ready := Bool(false) io.dptw.req.valid := Bool(false) io.iptw.req.valid := Bool(false) io.pptw.req.valid := Bool(false) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 09c4f006..86582cff 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -13,7 +13,7 @@ case object BuildRoCC extends Field[Seq[RoccParameters]] case class RoccParameters( opcodes: OpcodeSet, generator: Parameters => RoCC, - nMemChannels: Int = 1, + nMemChannels: Int = 0, useFPU: Boolean = false) abstract class Tile(resetSignal: Bool = null) @@ -63,8 +63,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile( // If so specified, build an RoCC module and wire it to core + TileLink ports, // otherwise just hookup the icache io.uncached <> (if (usingRocc) { - val iMemArb = Module(new ClientTileLinkIOArbiter(1 + nRocc)) - iMemArb.io.in(0) <> icache.io.mem + val uncachedArb = Module(new ClientTileLinkIOArbiter(1 + nRocc)) + uncachedArb.io.in(0) <> icache.io.mem val respArb = Module(new RRArbiter(new RoCCResponse, nRocc)) core.io.rocc.resp <> respArb.io.out @@ -82,7 +82,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile( rocc.io.exception := core.io.rocc.exception dcIF.io.requestor <> rocc.io.mem dcArb.io.requestor(2 + i) <> dcIF.io.cache - iMemArb.io.in(1 + i) <> rocc.io.imem + uncachedArb.io.in(1 + i) <> rocc.io.autl ptw.io.requestor(2 + 3 * i) <> rocc.io.iptw ptw.io.requestor(3 + 3 * i) <> rocc.io.dptw ptw.io.requestor(4 + 3 * i) <> rocc.io.pptw @@ -108,7 +108,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile( core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _) respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp)) - roccs.flatMap(_.io.dmem) :+ iMemArb.io.out + roccs.flatMap(_.io.utl) :+ uncachedArb.io.out } else { Seq(icache.io.mem) }) if (!usingRocc || nFPUPorts == 0) {