From 3673365b0811c3e1f3456902c3bc9c7639a0ba9d Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 28 Mar 2016 13:26:04 -0700 Subject: [PATCH] switch back to Chisel2 for verilog build for now --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9401fbdd..e7ddf49b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -64,7 +64,7 @@ before_install: - export CXX=g++-4.8 CC=gcc-4.8 script: - - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3 + - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default