Merge pull request #794 from freechipsproject/xbar-debug

Deal with lots of sources more gracefully.

.travis.yml

@@ -45,7 +45,7 @@ jobs:
   include:
     - stage: prepare cache
       script:
-        - make tools verilator -C regression SUITE=none
+        - travis_wait 120 make tools verilator -C regression SUITE=none
       before_install:
         - export CXX=g++-4.8 CC=gcc-4.8
       before_cache:

src/main/scala/rocketchip/Periphery.scala

@@ -346,7 +346,11 @@ trait HasPeripheryErrorSlave extends HasSystemNetworks {
   private val config = p(ErrorConfig)
   private val maxXfer = min(config.address.map(_.alignment).max.toInt, 4096)
   val error = LazyModule(new TLError(config.address, peripheryBusConfig.beatBytes))
-  error.node := TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node)
+
+  // Override the default Parameters to exclude the TLMonitor between the Fragmenter and error slave.
+  // Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others.
+  private def sourceInfo(implicit x: chisel3.internal.sourceinfo.SourceInfo) = x
+  error.node.:=(TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node))(new WithoutTLMonitors ++ p, sourceInfo)
 }
 
 

src/main/scala/uncore/tilelink2/Monitor.scala

@@ -466,10 +466,21 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
   }
 
   def legalizeUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
-    legalizeADSource(bundle, edge)
+    val sourceBits = log2Ceil(edge.client.endSourceId)
-    if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
+    val tooBig = 14 // >16kB worth of flight information gets to be too much
+    if (sourceBits > tooBig) {
+      println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
+    } else {
+      legalizeADSource(bundle, edge)
+    }
+    if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB && edge.manager.endSinkId > 1) {
       // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
-      if (edge.manager.endSinkId > 1) legalizeDESink(bundle, edge)
+      val sinkBits = log2Ceil(edge.manager.endSinkId)
+      if (sinkBits > tooBig) {
+        println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
+      } else {
+        legalizeDESink(bundle, edge)
+      }
     }
   }
 

src/main/scala/uncore/tilelink2/Xbar.scala

@@ -84,7 +84,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
     val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
     val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
 
-    // Print the mapping
+    // Print the address mapping
     if (false) {
       println("Xbar mapping:")
       route_addrs.foreach { p =>
@@ -95,6 +95,15 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
       println("--")
     }
 
+    // Print the ID mapping
+    if (false) {
+      println(s"XBar ${name} mapping:")
+      (node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
+        println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
+      }
+      println("")
+    }
+
     // We need an intermediate size of bundle with the widest possible identifiers
     val wide_bundle = io.in(0).params.union(io.out(0).params)