From 8264c0a77e1af7a5e6f61553f337c3f8179f1f4f Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 13 Jun 2017 14:32:35 -0700 Subject: [PATCH 1/4] add a debug print for xbar id mappings --- src/main/scala/uncore/tilelink2/Xbar.scala | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala index b4eef8dc..b331fcad 100644 --- a/src/main/scala/uncore/tilelink2/Xbar.scala +++ b/src/main/scala/uncore/tilelink2/Xbar.scala @@ -84,7 +84,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)) - // Print the mapping + // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => @@ -95,6 +95,15 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame println("--") } + // Print the ID mapping + if (false) { + println(s"XBar ${name} mapping:") + (node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => + println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") + } + println("") + } + // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = io.in(0).params.union(io.out(0).params) From 94f85e8bc877adb6cefda2abe45f95f834056c0e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 13 Jun 2017 15:35:22 -0700 Subject: [PATCH 2/4] tilelink2: TLMonitor will not create giant wires --- src/main/scala/uncore/tilelink2/Monitor.scala | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index b911d412..1d5eb3db 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -466,10 +466,21 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) } def legalizeUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) { - legalizeADSource(bundle, edge) - if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { + val sourceBits = log2Ceil(edge.client.endSourceId) + val tooBig = 14 // >16kB worth of flight information gets to be too much + if (sourceBits > tooBig) { + println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") + } else { + legalizeADSource(bundle, edge) + } + if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB && edge.manager.endSinkId > 1) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... - if (edge.manager.endSinkId > 1) legalizeDESink(bundle, edge) + val sinkBits = log2Ceil(edge.manager.endSinkId) + if (sinkBits > tooBig) { + println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") + } else { + legalizeDESink(bundle, edge) + } } } From b4b165112cc64354a31c834739576efc8155551d Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 13 Jun 2017 16:04:57 -0700 Subject: [PATCH 3/4] PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave This edge has the largest number of source bits by far. Let's just exclude it. --- src/main/scala/rocketchip/Periphery.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 91c87ceb..fa817d5e 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -346,7 +346,11 @@ trait HasPeripheryErrorSlave extends HasSystemNetworks { private val config = p(ErrorConfig) private val maxXfer = min(config.address.map(_.alignment).max.toInt, 4096) val error = LazyModule(new TLError(config.address, peripheryBusConfig.beatBytes)) - error.node := TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node) + + // Override the default Parameters to exclude the TLMonitor between the Fragmenter and error slave. + // Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others. + private def sourceInfo(implicit x: chisel3.internal.sourceinfo.SourceInfo) = x + error.node.:=(TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node))(new WithoutTLMonitors ++ p, sourceInfo) } From c85486e67ca9ea8899a7a5f987b634d2d5728052 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 13 Jun 2017 16:57:37 -0700 Subject: [PATCH 4/4] travis: don't give up if gcc is slow to build riscv-tools --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index ebc66eed..8d83cec2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -45,7 +45,7 @@ jobs: include: - stage: prepare cache script: - - make tools verilator -C regression SUITE=none + - travis_wait 120 make tools verilator -C regression SUITE=none before_install: - export CXX=g++-4.8 CC=gcc-4.8 before_cache: