cache optimizations, cleanup, and testharness improvement
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91c252ad08
commit
35af912bd2
@ -196,6 +196,7 @@ class rocketCtrl extends Component
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val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
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val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
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// FIXME
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// FIXME
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// io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
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io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
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io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
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val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
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val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
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@ -251,12 +251,14 @@ class rocketDCacheDM(lines: Int) extends Component {
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.we := tag_we;
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tag_array.io.we := tag_we;
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.ce := (state === s_ready) || (state === s_start_writeback) || (state === s_writeback);
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tag_array.io.ce :=
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(io.cpu.req_val && io.cpu.req_rdy) ||
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(state === s_start_writeback) ||
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(state === s_writeback);
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val tag_rdata = tag_array.io.q;
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val tag_rdata = tag_array.io.q;
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// valid bit array
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_array = Reg(resetVal = Bits(0, lines));
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// val vb_rdata = Reg(vb_array(tag_raddr));
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when (tag_we && !r_req_flush) {
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when (tag_we && !r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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}
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@ -265,9 +267,10 @@ class rocketDCacheDM(lines: Int) extends Component {
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}
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}
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val vb_rdata = Reg(vb_array(tag_addr).toBool);
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val vb_rdata = Reg(vb_array(tag_addr).toBool);
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val tag_valid = r_cpu_req_val && vb_rdata;
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val tag_valid = r_cpu_req_val && vb_rdata;
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// val tag_valid = Reg(vb_array(tag_addr)).toBool;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetbits) === p_store_idx(PGIDX_BITS-1,offsetbits));
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// load/store addresses conflict if they are to any part of the same 64 bit word
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val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetlsb) === p_store_idx(PGIDX_BITS-1,offsetlsb));
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val ldst_conflict = r_cpu_req_val && r_req_load && p_store_valid && addr_match;
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val ldst_conflict = r_cpu_req_val && r_req_load && p_store_valid && addr_match;
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// write the pending store data when the cache is idle, when the next command isn't a load
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// write the pending store data when the cache is idle, when the next command isn't a load
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@ -281,7 +284,6 @@ class rocketDCacheDM(lines: Int) extends Component {
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// dirty bit array
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// dirty bit array
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val db_array = Reg(resetVal = Bits(0, lines));
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val db_array = Reg(resetVal = Bits(0, lines));
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// val db_rdata = Reg(db_array(tag_raddr));
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val tag_dirty = Reg(db_array(tag_addr)).toBool;
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val tag_dirty = Reg(db_array(tag_addr)).toBool;
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when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
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when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
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@ -328,7 +330,6 @@ class rocketDCacheDM(lines: Int) extends Component {
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data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
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data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
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data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
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data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
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data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
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data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
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// data_array.io.ce := Bool(true); // FIXME
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data_array.io.ce :=
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data_array.io.ce :=
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(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
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(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
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(state === s_start_writeback) ||
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(state === s_start_writeback) ||
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@ -91,19 +91,7 @@ class rocketICacheDM(lines: Int) extends Component {
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r_cpu_req_val <== Bool(false);
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r_cpu_req_val <== Bool(false);
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}
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}
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// val r_cpu_req_addr = Reg(Bits(0, addrbits));
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// refill counter
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// when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
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// r_cpu_req_addr <== io.cpu.req_addr;
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// }
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// val r_cpu_req_val = Reg(Bool(false));
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// when ((state === s_ready) || (state === s_resolve_miss)) {
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// r_cpu_req_val <== io.cpu.req_val;
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// }
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// otherwise {
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// r_cpu_req_val <== Bool(false);
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// }
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val refill_count = Reg(resetVal = UFix(0,2));
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val refill_count = Reg(resetVal = UFix(0,2));
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when (io.mem.resp_val) {
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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refill_count <== refill_count + UFix(1);
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@ -119,12 +107,11 @@ class rocketICacheDM(lines: Int) extends Component {
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.we := tag_we;
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tag_array.io.we := tag_we;
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.ce := (state === s_ready) && io.cpu.req_val;
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tag_array.io.ce := (io.cpu.req_val && io.cpu.req_rdy);
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val tag_rdata = tag_array.io.q;
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val tag_rdata = tag_array.io.q;
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// valid bit array
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_array = Reg(resetVal = Bits(0, lines));
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// val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
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when (tag_we) {
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when (tag_we) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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}
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@ -140,7 +127,6 @@ class rocketICacheDM(lines: Int) extends Component {
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data_array.io.d := io.mem.resp_data;
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data_array.io.d := io.mem.resp_data;
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data_array.io.we := io.mem.resp_val;
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data_array.io.we := io.mem.resp_val;
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data_array.io.bweb := ~Bits(0,128);
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data_array.io.bweb := ~Bits(0,128);
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// data_array.io.ce := Bool(true); // FIXME
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data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss);
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data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss);
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val data_array_rdata = data_array.io.q;
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val data_array_rdata = data_array.io.q;
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@ -156,7 +142,6 @@ class rocketICacheDM(lines: Int) extends Component {
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io.mem.req_val := (state === s_request);
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io.mem.req_val := (state === s_request);
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
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// Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix;
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// control state machine
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// control state machine
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switch (state) {
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switch (state) {
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