riscv/rocket-chip
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cache optimizations, cleanup, and testharness improvement

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This commit is contained in:
Rimas Avizienis
2011-11-12 22:13:29 -08:00
parent 91c252ad08
commit 35af912bd2
3 changed files with 10 additions and 23 deletions
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rocket/src/main/scala/ctrl.scala
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@ -196,6 +196,7 @@ class rocketCtrl extends Component
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
// FIXME
// io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;