riscv/rocket-chip
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).

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Stephen Twigg committed 2013-09-24 10:54:09 -07:00
1 parent db1e09f0d0
commit 3532ae0b79
2 files changed
+7 -10
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rocket/src/main/scala/ctrl.scala
+1 -1
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@@ -595,7 +595,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
}
val sboard = new Scoreboard(32)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
val id_stall_fpu = if (conf.fpu) {