From 3532ae0b79ac3ebe70bf877e019fa0c184981674 Mon Sep 17 00:00:00 2001
From: Stephen Twigg <sdtwigg@eecs.berkeley.edu>
Date: Tue, 24 Sep 2013 10:54:09 -0700
Subject: [PATCH] From Andrew, actually mark scoreboard when rocc instruction
 with a writeback is issued. Also, fix an issue with AccumulatorExample not
 properly tagging its memory requests. Finally, reverted changes from f27429c
 to more properly follow the spike model (always return previous value of
 accumulator).

---
 rocket/src/main/scala/ctrl.scala |  2 +-
 rocket/src/main/scala/rocc.scala | 15 ++++++---------
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 60fb8dd7..90dcbd36 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -595,7 +595,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   }
 
   val sboard = new Scoreboard(32)
-  sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr)
+  sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
   sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
 
   val id_stall_fpu = if (conf.fpu) {
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index 543ce559..b1ca5956 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -91,24 +91,21 @@ class AccumulatorExample(conf: RocketConfiguration) extends RoCC(conf)
   val stallLoad = doLoad && !io.mem.req.ready
   val stallResp = doResp && !io.resp.ready
 
-  val loadSent = Reg(init=Bool(false))
-  when(cmd.fire()) { loadSent := Bool(false) }.elsewhen(io.mem.req.fire()) {loadSent := Bool(true)}
-    // This ensures that, even if we hold a command at the queue, it is only processed once
-
-  cmd.ready := !stallReg && !stallLoad && !stallResp && (!doLoad || !doResp || loadSent)
+  cmd.ready := !stallReg && !stallLoad && !stallResp
     // command resolved if no stalls AND not issuing a load that will need a request
     // note, loadSent = true will occur when the load response comes back
 
-  io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad && (!doLoad || loadSent)
-    // valid response if valid command, need a response, no stalls on needed reg AND not issuing a load
+  io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
+    // valid response if valid command, need a response, and no stalls
   io.resp.bits.rd := cmd.bits.inst.rd
-  io.resp.bits.data := accum
+  io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value
 
   io.busy := Bool(false)
   io.interrupt := Bool(false)
 
-  io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp && !loadSent
+  io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
   io.mem.req.bits.addr := addend
+  io.mem.req.bits.tag := addr
   io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
   io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
   io.mem.req.bits.data := Bits(0) // we're not performing any stores...