riscv/rocket-chip
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bootrom: follow SBI (a0=hartid, a1=dtb)

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This commit is contained in:
Wesley W. Terpstra 2017-03-24 15:55:57 -07:00
parent 9a2f0d01a1
commit 34f8ce653a
7 changed files with 36 additions and 28 deletions
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9
bootrom/Makefile
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@ -5,8 +5,11 @@ OBJCOPY=riscv64-unknown-elf-objcopy
all: $(bootrom_img) all: $(bootrom_img)
%.img: %.elf %.img: %.bin
$(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@ dd if=$< of=$@ bs=128 count=1
%.bin: %.elf
$(OBJCOPY) -O binary $< $@
%.elf: %.S linker.ld %.elf: %.S linker.ld
$(GCC) -Tlinker.ld $< -nostdlib -static -o $@ $(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@

30
bootrom/bootrom.S
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@ -1,13 +1,19 @@
.text .section .text.start, "ax", @progbits
.global _start .globl _start
_start: _start:
// This boot ROM doesn't know about any boot devices, so it just spins, la s0, DRAM_BASE
// waiting for the debugger to load a program and change the PC. csrr a0, mhartid
j _start // reset vector la a1, _dtb
.word 0 // reserved jr s0
.word 0 // reserved
.word 0 // pointer to config string .section .text.hang, "ax", @progbits
.word 0 // default trap vector .globl _hang
.word 0 _hang:
.word 0 wfi
.word 0 j _hang
.section .rodata.dtb, "a", @progbits
.globl _dtb
.align 5, 0
_dtb:
.ascii "DTB goes here"

BIN
bootrom/bootrom.img Executable file → Normal file
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Binary file not shown.

11
bootrom/linker.ld
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@ -1,5 +1,12 @@
SECTIONS SECTIONS
{ {
. = 0x1000; DRAM_BASE = 0x80000000;
.text : { *(.text) } ROM_BASE = 0x1000;
. = ROM_BASE;
.text.start : { *(.text.start) }
. = ROM_BASE + 0x40;
.text.hang : { *(.text.hang) }
. = ROM_BASE + 0x80;
.rodata.dtb : { *(.rodata.dtb) }
} }

2
src/main/scala/rocketchip/Periphery.scala
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@ -307,7 +307,7 @@ trait PeripheryBootROM {
private val bootrom_address = 0x1000 private val bootrom_address = 0x1000
private val bootrom_size = 0x1000 private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dtb) private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes)) val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
} }

2
src/main/scala/rocketchip/RISCVPlatform.scala
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@ -124,5 +124,5 @@ trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
val outer: HardwiredResetVector val outer: HardwiredResetVector
val io: HardwiredResetVectorBundle val io: HardwiredResetVectorBundle
outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM outer.coreplex.module.io.resetVector := UInt(0x1040) // boot ROM: hang
} }

10
src/main/scala/rocketchip/Utils.scala
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@ -53,17 +53,9 @@ class GlobalVariable[T] {
} }
object GenerateBootROM { object GenerateBootROM {
def apply(p: Parameters, address: BigInt, dtb: DTB) = { def apply(dtb: DTB)(implicit p: Parameters) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile))) val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata) val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
require(address == address.toInt)
val dtbAddr = address.toInt + rom.capacity
require(rom.getInt(12) == 0,
"DTS address position should not be occupied by code")
rom.putInt(12, dtbAddr)
rom.array() ++ dtb.contents rom.array() ++ dtb.contents
} }
} }