From 34f8ce653a4ab7aaf27d33b1c87fc638d2582009 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 24 Mar 2017 15:55:57 -0700
Subject: [PATCH] bootrom: follow SBI (a0=hartid, a1=dtb)

---
 bootrom/Makefile                              |   9 ++++--
 bootrom/bootrom.S                             |  30 +++++++++++-------
 bootrom/bootrom.img                           | Bin 32 -> 128 bytes
 bootrom/linker.ld                             |  11 +++++--
 src/main/scala/rocketchip/Periphery.scala     |   2 +-
 src/main/scala/rocketchip/RISCVPlatform.scala |   2 +-
 src/main/scala/rocketchip/Utils.scala         |  10 +-----
 7 files changed, 36 insertions(+), 28 deletions(-)
 mode change 100755 => 100644 bootrom/bootrom.img

diff --git a/bootrom/Makefile b/bootrom/Makefile
index 3ea5f831..0580ba5a 100644
--- a/bootrom/Makefile
+++ b/bootrom/Makefile
@@ -5,8 +5,11 @@ OBJCOPY=riscv64-unknown-elf-objcopy
 
 all: $(bootrom_img)
 
-%.img: %.elf
-	$(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@
+%.img: %.bin
+	dd if=$< of=$@ bs=128 count=1
+
+%.bin: %.elf
+	$(OBJCOPY) -O binary $< $@
 
 %.elf: %.S linker.ld
-	$(GCC) -Tlinker.ld $< -nostdlib -static -o $@
+	$(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@
diff --git a/bootrom/bootrom.S b/bootrom/bootrom.S
index b35ee02a..384a4a37 100644
--- a/bootrom/bootrom.S
+++ b/bootrom/bootrom.S
@@ -1,13 +1,19 @@
-.text
-.global _start
+.section .text.start, "ax", @progbits
+.globl _start
 _start:
-  // This boot ROM doesn't know about any boot devices, so it just spins,
-  // waiting for the debugger to load a program and change the PC.
-  j _start // reset vector
-  .word 0 // reserved
-  .word 0 // reserved
-  .word 0 // pointer to config string
-  .word 0 // default trap vector
-  .word 0
-  .word 0
-  .word 0
+  la s0, DRAM_BASE
+  csrr a0, mhartid
+  la a1, _dtb
+  jr s0
+
+.section .text.hang, "ax", @progbits
+.globl _hang
+_hang:
+  wfi
+  j _hang
+
+.section .rodata.dtb, "a", @progbits
+.globl _dtb
+.align 5, 0
+_dtb:
+.ascii "DTB goes here"
diff --git a/bootrom/bootrom.img b/bootrom/bootrom.img
old mode 100755
new mode 100644
index 6d852f38bd3cd969a84d637805f29967f4d35926..c2016e2b9acdc66add405958d963c1e811ad0020
GIT binary patch
literal 128
rcmWgt^1oh~g@vJ5)#2lGRtAR2t*-1$Eeu41Vuk>LultEsj-e0$(=rKr

literal 32
Kcmd02zz+Zp003|R

diff --git a/bootrom/linker.ld b/bootrom/linker.ld
index 1b6ff96d..d209bc93 100644
--- a/bootrom/linker.ld
+++ b/bootrom/linker.ld
@@ -1,5 +1,12 @@
 SECTIONS
 {
-    . = 0x1000;
-    .text : { *(.text) }
+    DRAM_BASE = 0x80000000;
+    ROM_BASE = 0x1000;
+
+    . = ROM_BASE;
+    .text.start : { *(.text.start) }
+    . = ROM_BASE + 0x40;
+    .text.hang : { *(.text.hang) }
+    . = ROM_BASE + 0x80;
+    .rodata.dtb : { *(.rodata.dtb) }
 }
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 4d091e80..2a98f30f 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -307,7 +307,7 @@ trait PeripheryBootROM {
 
   private val bootrom_address = 0x1000
   private val bootrom_size = 0x1000
-  private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dtb)
+  private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
   val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
   bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
 }
diff --git a/src/main/scala/rocketchip/RISCVPlatform.scala b/src/main/scala/rocketchip/RISCVPlatform.scala
index 7bc9779a..27f511d7 100644
--- a/src/main/scala/rocketchip/RISCVPlatform.scala
+++ b/src/main/scala/rocketchip/RISCVPlatform.scala
@@ -124,5 +124,5 @@ trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
   val outer: HardwiredResetVector
   val io: HardwiredResetVectorBundle
 
-  outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
+  outer.coreplex.module.io.resetVector := UInt(0x1040) // boot ROM: hang
 }
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index c6910d69..f6d039d8 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -53,17 +53,9 @@ class GlobalVariable[T] {
 }
 
 object GenerateBootROM {
-  def apply(p: Parameters, address: BigInt, dtb: DTB) = {
+  def apply(dtb: DTB)(implicit p: Parameters) = {
     val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
     val rom = ByteBuffer.wrap(romdata)
-
-    rom.order(ByteOrder.LITTLE_ENDIAN)
-
-    require(address == address.toInt)
-    val dtbAddr = address.toInt + rom.capacity
-    require(rom.getInt(12) == 0,
-      "DTS address position should not be occupied by code")
-    rom.putInt(12, dtbAddr)
     rom.array() ++ dtb.contents
   }
 }