riscv/rocket-chip
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bootrom: follow SBI (a0=hartid, a1=dtb)

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This commit is contained in:
Wesley W. Terpstra
2017-03-24 15:55:57 -07:00
parent 9a2f0d01a1
commit 34f8ce653a
7 changed files with 36 additions and 28 deletions
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2
src/main/scala/rocketchip/Periphery.scala
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@ -307,7 +307,7 @@ trait PeripheryBootROM {
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dtb)
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}

2
src/main/scala/rocketchip/RISCVPlatform.scala
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@ -124,5 +124,5 @@ trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
val outer: HardwiredResetVector
val io: HardwiredResetVectorBundle
outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
outer.coreplex.module.io.resetVector := UInt(0x1040) // boot ROM: hang
}

10
src/main/scala/rocketchip/Utils.scala
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@ -53,17 +53,9 @@ class GlobalVariable[T] {
}
object GenerateBootROM {
def apply(p: Parameters, address: BigInt, dtb: DTB) = {
def apply(dtb: DTB)(implicit p: Parameters) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
require(address == address.toInt)
val dtbAddr = address.toInt + rom.capacity
require(rom.getInt(12) == 0,
"DTS address position should not be occupied by code")
rom.putInt(12, dtbAddr)
rom.array() ++ dtb.contents
}
}