set missing port direction
Ideally, chisel should flag this as an error.
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@ -21,7 +21,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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val io = new Bundle {
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val imem = Decoupled(new FrontendResp).flip
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val kill = Bool(INPUT)
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val pc = UInt(width = vaddrBitsExtended)
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val pc = UInt(OUTPUT, vaddrBitsExtended)
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val btb_resp = new BTBResp().asOutput
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val inst = Vec(retireWidth, Decoupled(new Instruction))
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}
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