From 33eaf08b60b103ecfe2081f1fc6c001c8029bbdf Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 25 Aug 2016 19:33:03 -0700
Subject: [PATCH] set missing port direction

Ideally, chisel should flag this as an error.
---
 src/main/scala/rocket/ibuf.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/rocket/ibuf.scala b/src/main/scala/rocket/ibuf.scala
index afc8154c..c5a275fd 100644
--- a/src/main/scala/rocket/ibuf.scala
+++ b/src/main/scala/rocket/ibuf.scala
@@ -21,7 +21,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
   val io = new Bundle {
     val imem = Decoupled(new FrontendResp).flip
     val kill = Bool(INPUT)
-    val pc = UInt(width = vaddrBitsExtended)
+    val pc = UInt(OUTPUT, vaddrBitsExtended)
     val btb_resp = new BTBResp().asOutput
     val inst = Vec(retireWidth, Decoupled(new Instruction))
   }