riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

set missing port direction

Browse Source 
Ideally, chisel should flag this as an error.
This commit is contained in:
Andrew Waterman
2016-08-25 19:33:03 -07:00
parent a19bd6de96
commit 33eaf08b60
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/ibuf.scala
View File

@@ -21,7 +21,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
val io = new Bundle { val io = new Bundle {
val imem = Decoupled(new FrontendResp).flip val imem = Decoupled(new FrontendResp).flip
val kill = Bool(INPUT) val kill = Bool(INPUT)
val pc = UInt(width = vaddrBitsExtended) val pc = UInt(OUTPUT, vaddrBitsExtended)
val btb_resp = new BTBResp().asOutput val btb_resp = new BTBResp().asOutput
val inst = Vec(retireWidth, Decoupled(new Instruction)) val inst = Vec(retireWidth, Decoupled(new Instruction))
} }