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hasti: fix test SRAM depth

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This commit is contained in:
Wesley W. Terpstra 2016-06-08 13:25:11 -07:00
parent 0969be8804
commit 3393d4362b
1 changed files with 2 additions and 2 deletions
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4
junctions/src/main/scala/hasti.scala
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@ -474,7 +474,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
// The mask and address during the address phase // The mask and address during the address phase
val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ) val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
val a_mask = Wire(UInt(width = hastiDataBytes)) val a_mask = Wire(UInt(width = hastiDataBytes))
val a_address = io.haddr >> UInt(hastiAlignment) val a_address = io.haddr(depth-1, hastiAlignment)
val a_write = io.hwrite val a_write = io.hwrite
// for backwards compatibility with chisel2, we needed a static width in definition // for backwards compatibility with chisel2, we needed a static width in definition
@ -507,7 +507,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
val p_wdata = holdUnless(d_wdata, p_latch_d) val p_wdata = holdUnless(d_wdata, p_latch_d)
// Use single-ported memory with byte-write enable // Use single-ported memory with byte-write enable
val mem = SeqMem(depth, Vec(hastiDataBytes, Bits(width = 8))) val mem = SeqMem(1 << (depth-hastiAlignment), Vec(hastiDataBytes, Bits(width = 8)))
// Decide is the SRAM port is used for reading or (potentially) writing // Decide is the SRAM port is used for reading or (potentially) writing
val read = ready && a_request && !a_write val read = ready && a_request && !a_write