diff --git a/groundtest/src/main/scala/CacheFillTest.scala b/groundtest/src/main/scala/CacheFillTest.scala
index ac6a5c54..4e96a5da 100644
--- a/groundtest/src/main/scala/CacheFillTest.scala
+++ b/groundtest/src/main/scala/CacheFillTest.scala
@@ -4,6 +4,7 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
+import uncore.util._
 import cde.{Parameters, Field}
 
 class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
@@ -13,7 +14,7 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
   val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
   val state = Reg(init = s_start)
 
-  val active = state === s_prefetch || state === s_retrieve
+  val active = state.isOneOf(s_prefetch, s_retrieve)
 
   val xact_pending = Reg(init = UInt(0, tlMaxClientXacts))
   val xact_id = PriorityEncoder(~xact_pending)
diff --git a/groundtest/src/main/scala/Regression.scala b/groundtest/src/main/scala/Regression.scala
index cc347ad6..00417b14 100644
--- a/groundtest/src/main/scala/Regression.scala
+++ b/groundtest/src/main/scala/Regression.scala
@@ -4,6 +4,7 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
+import uncore.util._
 import junctions.{ParameterizedBundle, HasAddrMapParameters, Timer}
 import rocket.HellaCacheIO
 import cde.{Parameters, Field}
@@ -159,7 +160,7 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
     client_xact_id = UInt(2),
     addr_block = addr_block)
 
-  io.mem.acquire.valid := (state === s_prefetch) || (state === s_get) || (state === s_put)
+  io.mem.acquire.valid := state.isOneOf(s_prefetch, s_get, s_put)
   io.mem.acquire.bits := MuxCase(get_acq, Seq(
     (state === s_prefetch) -> prefetch_acq,
     (state === s_put) -> put_acq))
@@ -235,11 +236,11 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
     addr_block = test_block(get_acq_id),
     addr_beat = test_beat(get_acq_id))
 
-  io.mem.acquire.valid := (state === s_pf_send) || (state === s_put_send) || (state === s_get_send)
+  io.mem.acquire.valid := state.isOneOf(s_pf_send, s_put_send, s_get_send)
   io.mem.acquire.bits := MuxLookup(state, pf_acquire, Seq(
     s_put_send -> put_acquire,
     s_get_send -> get_acquire))
-  io.mem.grant.ready := (state === s_pf_wait) || (state === s_put_wait) || (state === s_get_wait)
+  io.mem.grant.ready := state.isOneOf(s_pf_wait, s_put_wait, s_get_wait)
 
   when (state === s_idle && io.start) { state := s_pf_send }
   when (state === s_pf_send && io.mem.acquire.ready) { state := s_pf_wait }
@@ -321,9 +322,9 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
     client_xact_id = UInt(0),
     addr_block = UInt(memStartBlock + 6) + stage)
 
-  io.mem.acquire.valid := (state === s_put_send || state === s_get_send)
+  io.mem.acquire.valid := state.isOneOf(s_put_send, s_get_send)
   io.mem.acquire.bits := Mux(state === s_get_send, get_acq, put_acq)
-  io.mem.grant.ready := (state === s_put_ack || state === s_get_ack)
+  io.mem.grant.ready := state.isOneOf(s_put_ack, s_get_ack)
 
   val (get_cnt, get_done) = Counter(
     io.mem.grant.fire() && gnt.hasData(), tlDataBeats)
@@ -491,7 +492,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
   val s_idle :: s_write :: s_read :: s_done :: Nil = Enum(Bits(), 4)
   val state = Reg(init = s_idle)
 
-  io.cache.req.valid := sending && (state === s_write || state === s_read)
+  io.cache.req.valid := sending && state.isOneOf(s_write, s_read)
   io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset))
   io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
   io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
@@ -544,7 +545,7 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
 
   val (ack_cnt, all_acked) = Counter(io.mem.grant.fire(), 2)
 
-  io.mem.acquire.valid := (state === s_put) || (state === s_putblock)
+  io.mem.acquire.valid := state.isOneOf(s_put, s_putblock)
   io.mem.acquire.bits := Mux(state === s_put, put_acquire, put_block_acquire)
   io.mem.grant.ready := (state === s_wait)
 
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 51f1e3c1..f51a121e 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -349,7 +349,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
   val wen = cpu_wen && !read_only
 
-  val wdata = (Mux((io.rw.cmd === CSR.S || io.rw.cmd === CSR.C), io.rw.rdata, UInt(0)) |
+  val wdata = (Mux(io.rw.cmd.isOneOf(CSR.S, CSR.C), io.rw.rdata, UInt(0)) |
                Mux(io.rw.cmd =/= CSR.C, io.rw.wdata, UInt(0))) &
               ~Mux(io.rw.cmd === CSR.C, io.rw.wdata, UInt(0))
 
diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index 352e8140..2b93381a 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -88,7 +88,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val release_state = Reg(init=s_ready)
   val pstore1_valid = Wire(Bool())
   val pstore2_valid = Reg(Bool())
-  val inWriteback = release_state === s_voluntary_writeback || release_state === s_probe_rep_dirty
+  val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty)
   val releaseWay = Wire(UInt())
   io.cpu.req.ready := (release_state === s_ready) && !grant_wait && !s1_nack
 
@@ -345,14 +345,14 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     }
   }
   when (releaseDone) { release_state := s_ready }
-  when (release_state === s_probe_rep_miss || release_state === s_probe_rep_clean) {
+  when (release_state.isOneOf(s_probe_rep_miss, s_probe_rep_clean)) {
     io.mem.release.valid := true
   }
-  when (release_state === s_probe_rep_clean || release_state === s_probe_rep_dirty) {
+  when (release_state.isOneOf(s_probe_rep_clean, s_probe_rep_dirty)) {
     io.mem.release.bits := probeResponseMessage
     when (releaseDone) { release_state := s_probe_write_meta }
   }
-  when (release_state === s_voluntary_writeback || release_state === s_voluntary_write_meta) {
+  when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
     io.mem.release.bits := voluntaryReleaseMessage
     newCoh := voluntaryNewCoh
     releaseWay := s2_victim_way
@@ -371,7 +371,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   dataArb.io.in(2).bits.addr := Cat(io.mem.release.bits.addr_block, releaseDataBeat(log2Up(refillCycles)-1,0)) << rowOffBits
   dataArb.io.in(2).bits.way_en := ~UInt(0, nWays)
 
-  metaWriteArb.io.in(2).valid := (release_state === s_voluntary_write_meta || release_state === s_probe_write_meta)
+  metaWriteArb.io.in(2).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta)
   metaWriteArb.io.in(2).bits.way_en := releaseWay
   metaWriteArb.io.in(2).bits.idx := io.mem.release.bits.full_addr()(idxMSB, idxLSB)
   metaWriteArb.io.in(2).bits.data.coh := newCoh
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index f5e22fc2..f310bd55 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -282,12 +282,6 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(UInt(), 9)
   val state = Reg(init=s_invalid)
 
-  def stateIsOneOf(check_states: Seq[UInt]): Bool =
-    check_states.map(state === _).reduce(_ || _)
-
-  def stateIsOneOf(st1: UInt, st2: UInt*): Bool =
-    stateIsOneOf(st1 +: st2)
-
   val new_coh_state = Reg(init=ClientMetadata.onReset)
   val req = Reg(new MSHRReqInternal())
   val req_idx = req.addr(untagBits-1,blockOffBits)
@@ -306,14 +300,14 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val (refill_cnt, refill_count_done) = Counter(io.mem_grant.valid && gnt_multi_data, refillCycles)
   val refill_done = io.mem_grant.valid && (!gnt_multi_data || refill_count_done)
   val sec_rdy = idx_match &&
-                  (stateIsOneOf(states_before_refill) ||
-                    (stateIsOneOf(s_refill_req, s_refill_resp) &&
+                  (state.isOneOf(states_before_refill) ||
+                    (state.isOneOf(s_refill_req, s_refill_resp) &&
                       !cmd_requires_second_acquire && !refill_done))
 
   val rpq = Module(new Queue(new ReplayInternal, p(ReplayQueueDepth)))
   rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd)
   rpq.io.enq.bits := io.req_bits
-  rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
+  rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid
 
   val coh_on_grant = req.old_meta.coh.onGrant(
                           incoming = io.mem_grant.bits,
@@ -373,7 +367,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
 
   val fq = Module(new FinishQueue(1))
   val g = io.mem_grant.bits
-  val can_finish = state === s_invalid || state === s_refill_req
+  val can_finish = state.isOneOf(s_invalid, s_refill_req)
   fq.io.enq.valid := io.mem_grant.valid && g.requiresAck() && refill_done
   fq.io.enq.bits := g.makeFinish()
   io.mem_finish.valid := fq.io.deq.valid && can_finish
@@ -390,9 +384,9 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val meta_hazard = Reg(init=UInt(0,2))
   when (meta_hazard =/= UInt(0)) { meta_hazard := meta_hazard + 1 }
   when (io.meta_write.fire()) { meta_hazard := 1 }
-  io.probe_rdy := !idx_match || (!stateIsOneOf(states_before_refill) && meta_hazard === 0) 
+  io.probe_rdy := !idx_match || (!state.isOneOf(states_before_refill) && meta_hazard === 0) 
 
-  io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear
+  io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear)
   io.meta_write.bits.idx := req_idx
   io.meta_write.bits.data.coh := Mux(state === s_meta_clear,
                                       req.old_meta.coh.onCacheControl(M_FLUSH),
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 9d745cec..d714fce1 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -130,7 +130,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   pte_wdata.a := true
   pte_wdata.d := r_req.store
   
-  io.mem.req.valid     := state === s_req || state === s_set_dirty
+  io.mem.req.valid     := state.isOneOf(s_req, s_set_dirty)
   io.mem.req.bits.phys := Bool(true)
   io.mem.req.bits.cmd  := Mux(state === s_set_dirty, M_XA_OR, M_XRD)
   io.mem.req.bits.typ  := log2Ceil(xLen/8)
diff --git a/uncore/src/main/scala/devices/Bram.scala b/uncore/src/main/scala/devices/Bram.scala
index 9fadadb8..9e360439 100644
--- a/uncore/src/main/scala/devices/Bram.scala
+++ b/uncore/src/main/scala/devices/Bram.scala
@@ -74,7 +74,7 @@ class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
     (0 until max_size).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1))))
   val wmask = (wmask_lut << waddr(max_size - 1, 0))(hastiDataBytes - 1, 0)
 
-  val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
+  val is_trans = io.hsel && io.htrans.isOneOf(HTRANS_NONSEQ, HTRANS_SEQ)
   val raddr = io.haddr >> UInt(max_size)
   val ren = is_trans && !io.hwrite
   val bypass = Reg(init = Bool(false))
diff --git a/uncore/src/main/scala/devices/Debug.scala b/uncore/src/main/scala/devices/Debug.scala
index 0a6ba944..531fa6a1 100644
--- a/uncore/src/main/scala/devices/Debug.scala
+++ b/uncore/src/main/scala/devices/Debug.scala
@@ -4,6 +4,7 @@ package uncore.devices
 
 import Chisel._
 import uncore.tilelink._
+import uncore.util._
 import junctions._
 import cde.{Parameters, Config, Field}
 
@@ -901,7 +902,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
   when (sbAddr(11, 8) === UInt(4)) {                                 //0x400-0x4FF Debug RAM
     sbRdData  := sbRamRdData
     sbRamRdEn := sbRdEn
-  }.elsewhen (sbAddr(11,8) === UInt(8) || sbAddr(11,8) === UInt(9)){ //0x800-0x9FF Debug ROM
+  }.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
     if (cfg.hasDebugRom) {
       sbRdData := sbRomRdData
     } else {
diff --git a/uncore/src/main/scala/unittests/Drivers.scala b/uncore/src/main/scala/unittests/Drivers.scala
index 09748a2a..a359207d 100644
--- a/uncore/src/main/scala/unittests/Drivers.scala
+++ b/uncore/src/main/scala/unittests/Drivers.scala
@@ -4,6 +4,7 @@ import Chisel._
 import junctions._
 import uncore.tilelink._
 import uncore.constants._
+import uncore.util._
 import cde.Parameters
 
 abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
@@ -167,7 +168,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
   val put_data = Fill(dataRep, put_cnt)(tlDataBits - 1, 0)
   val get_data = Fill(dataRep, get_cnt)(tlDataBits - 1, 0)
 
-  io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
+  io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
   io.mem.acquire.bits := Mux(state === s_put_req,
     Put(
       client_xact_id = UInt(0),
@@ -178,7 +179,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
       client_xact_id = UInt(0),
       addr_block = get_block,
       addr_beat = get_beat))
-  io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
+  io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
 
   when (state === s_idle && io.start) { state := s_put_req }
   when (state === s_put_req && io.mem.acquire.ready) { state := s_put_resp }
@@ -239,7 +240,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
   }
 
   io.finished := (state === s_done)
-  io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
+  io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
   io.mem.acquire.bits := Mux(state === s_put_req,
     Put(
       client_xact_id = UInt(0),
@@ -251,7 +252,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
       client_xact_id = UInt(0),
       addr_block = UInt(0),
       addr_beat = UInt(0)))
-  io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
+  io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
 
   assert(!io.mem.grant.valid || state =/= s_get_resp ||
          io.mem.grant.bits.data === expected,
@@ -295,9 +296,9 @@ class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
     addr_block = get_cnt)
 
   io.finished := (state === s_done)
-  io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
+  io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
   io.mem.acquire.bits := Mux(state === s_put_req, put_acquire, get_acquire)
-  io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
+  io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
 
   assert(!io.mem.grant.valid || state =/= s_get_resp ||
          io.mem.grant.bits.data === get_data,