riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3 compatibility fix

Browse Source 
No need for a Vec here.
This commit is contained in:
Andrew Waterman 2016-01-15 15:16:54 -08:00
parent c8fa7c43a9
commit 335fb73120
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
junctions/src/main/scala/nasti.scala
View File

@ -560,10 +560,11 @@ class NastiRecursiveInterconnect(
err_slave.io <> xbarSlave
} else {
val subSlaves = submap.countSlaves
val outputs = Vec(io.slaves.drop(slaveInd).take(subSlaves))
val outputs = io.slaves.drop(slaveInd).take(subSlaves)
val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
ic.io.masters.head <> xbarSlave
outputs <> ic.io.slaves
for ((o, s) <- outputs zip ic.io.slaves)
o <> s
slaveInd += subSlaves
}
case MemChannels(_, nchannels, _) =>