Fix testing of DefaultSmallConfig; bump rocket et al
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parent
8c13e78ab5
commit
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2
chisel3
2
chisel3
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Subproject commit 378edecbf797f19cf26f5a4d6a3ed3df701ba66d
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Subproject commit c90be4ea06faf9a39c85f38e932d29fe63eb4b37
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@ -52,7 +52,7 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
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# Run Verilator to produce a fast binary to emulate this circuit.
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# Run Verilator to produce a fast binary to emulate this circuit.
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VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
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VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
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VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
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-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT \
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-Wno-STMTDLY --x-assign unique \
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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2
firrtl
2
firrtl
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Subproject commit 5e6fac5d51bf62078d2319a0aae05807f82cf809
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Subproject commit b7de40e23161a7346fea90576f07b5c200c2675b
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Subproject commit a7c8c20300c1218b9d8f56c6f3d62f46b0359648
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Subproject commit 9eeefb6e859cb8b68a91065b00992949ef677fe6
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Subproject commit 40894cdde5de0c87b959663ce62535e47412a843
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Subproject commit 6953e5c4a32afd0055200578a3e7eda064f58859
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2
rocket
2
rocket
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Subproject commit fad901bdc023824dd7cd54d68ab91ac9a5a89a59
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Subproject commit d972677a0c07b6cdf6b806cbd4a152b103c3293c
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@ -179,7 +179,7 @@ class BaseConfig extends Config (
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else (rv32i, rv32u)
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else (rv32i, rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(bmarks)
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TestGeneration.addSuite(benchmarks)
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TLId => "L1toL2"
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case TLId => "L1toL2"
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@ -208,11 +208,11 @@ class BaseConfig extends Config (
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case XLen => 64
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case XLen => 64
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case UseFPU => {
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case UseFPU => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuite(rv32udBenchmarks)
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if(site(FDivSqrt)) {
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if(site(FDivSqrt)) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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} else {
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else {
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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}
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}
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@ -146,8 +146,11 @@ object DefaultTestSuites {
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val rv64u = List(rv64ui, rv64um)
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val rv64u = List(rv64ui, rv64um)
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val rv64i = List(rv64ui, rv64si, rv64mi)
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val rv64i = List(rv64ui, rv64si, rv64mi)
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val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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"median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))
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"median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))
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val rv32udBenchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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"mm", "spmv", "mt-vvadd"))
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val emptyBmarks = new BenchmarkTestSuite("empty",
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val emptyBmarks = new BenchmarkTestSuite("empty",
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"$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty)
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"$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty)
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 2109a48e18719383942d535ff4c1d0a859dcc424
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Subproject commit bc6679ecd5edfe8dbfa27e52d06651f7b8ae47dc
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@ -45,6 +45,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
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+incdir+$(generated_dir) \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+RANDOMIZE \
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+libext+.v \
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+libext+.v \
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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