From 32ee5432dd088628d81a5f555d9a941eb0a46184 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 7 Jul 2016 19:34:03 -0700
Subject: [PATCH] Fix testing of DefaultSmallConfig; bump rocket et al

---
 chisel3                      | 2 +-
 emulator/Makefrag-verilator  | 2 +-
 firrtl                       | 2 +-
 groundtest                   | 2 +-
 riscv-tools                  | 2 +-
 rocket                       | 2 +-
 src/main/scala/Configs.scala | 6 +++---
 src/main/scala/Testing.scala | 7 +++++--
 uncore                       | 2 +-
 vsim/Makefrag                | 1 +
 10 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/chisel3 b/chisel3
index 378edecb..c90be4ea 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 378edecbf797f19cf26f5a4d6a3ed3df701ba66d
+Subproject commit c90be4ea06faf9a39c85f38e932d29fe63eb4b37
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index c7945168..6a43f71c 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -52,7 +52,7 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
-	-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT \
+	-Wno-STMTDLY --x-assign unique \
   -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 
diff --git a/firrtl b/firrtl
index 5e6fac5d..b7de40e2 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 5e6fac5d51bf62078d2319a0aae05807f82cf809
+Subproject commit b7de40e23161a7346fea90576f07b5c200c2675b
diff --git a/groundtest b/groundtest
index a7c8c203..9eeefb6e 160000
--- a/groundtest
+++ b/groundtest
@@ -1 +1 @@
-Subproject commit a7c8c20300c1218b9d8f56c6f3d62f46b0359648
+Subproject commit 9eeefb6e859cb8b68a91065b00992949ef677fe6
diff --git a/riscv-tools b/riscv-tools
index 40894cdd..6953e5c4 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 40894cdde5de0c87b959663ce62535e47412a843
+Subproject commit 6953e5c4a32afd0055200578a3e7eda064f58859
diff --git a/rocket b/rocket
index fad901bd..d972677a 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit fad901bdc023824dd7cd54d68ab91ac9a5a89a59
+Subproject commit d972677a0c07b6cdf6b806cbd4a152b103c3293c
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 818a9e26..dec14179 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -179,7 +179,7 @@ class BaseConfig extends Config (
           else (rv32i, rv32u)
         TestGeneration.addSuites(rvi.map(_("p")))
         TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        TestGeneration.addSuite(bmarks)
+        TestGeneration.addSuite(benchmarks)
         List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
           Module(new RocketTile(resetSignal = r)(p.alterPartial({
             case TLId => "L1toL2"
@@ -208,11 +208,11 @@ class BaseConfig extends Config (
       case XLen => 64
       case UseFPU => {
         val env = if(site(UseVM)) List("p","v") else List("p")
+        TestGeneration.addSuite(rv32udBenchmarks)
         if(site(FDivSqrt)) {
           TestGeneration.addSuites(env.map(rv64uf))
           TestGeneration.addSuites(env.map(rv64ud))
-        }
-        else {
+        } else {
           TestGeneration.addSuites(env.map(rv64ufNoDiv))
           TestGeneration.addSuites(env.map(rv64udNoDiv))
         }
diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala
index f4cf72ad..4ed1854a 100644
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@@ -146,8 +146,11 @@ object DefaultTestSuites {
   val rv64u = List(rv64ui, rv64um)
   val rv64i = List(rv64ui, rv64si, rv64mi)
 
-  val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
-    "median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))
+  val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
+    "median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))
+
+  val rv32udBenchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
+    "mm", "spmv", "mt-vvadd"))
 
   val emptyBmarks = new BenchmarkTestSuite("empty",
     "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty)
diff --git a/uncore b/uncore
index 2109a48e..bc6679ec 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 2109a48e18719383942d535ff4c1d0a859dcc424
+Subproject commit bc6679ecd5edfe8dbfa27e52d06651f7b8ae47dc
diff --git a/vsim/Makefrag b/vsim/Makefrag
index 592728d2..7b5b8236 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -45,6 +45,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	+incdir+$(generated_dir) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
+	+define+RANDOMIZE \
 	+libext+.v \
 
 #--------------------------------------------------------------------