riscv/rocket-chip
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Fix testing of DefaultSmallConfig; bump rocket et al

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This commit is contained in:
Andrew Waterman
2016-07-07 19:34:03 -07:00
parent 8c13e78ab5
commit 32ee5432dd
10 changed files with 16 additions and 12 deletions
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6
src/main/scala/Configs.scala
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@ -179,7 +179,7 @@ class BaseConfig extends Config (
else (rv32i, rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(bmarks)
TestGeneration.addSuite(benchmarks)
List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
@ -208,11 +208,11 @@ class BaseConfig extends Config (
case XLen => 64
case UseFPU => {
val env = if(site(UseVM)) List("p","v") else List("p")
TestGeneration.addSuite(rv32udBenchmarks)
if(site(FDivSqrt)) {
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuites(env.map(rv64ud))
}
else {
} else {
TestGeneration.addSuites(env.map(rv64ufNoDiv))
TestGeneration.addSuites(env.map(rv64udNoDiv))
}