riscv/rocket-chip
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coreplex: include optional tile name for downstream name stabilization

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This commit is contained in:
Henry Cook 2017-08-30 15:23:10 -07:00
parent 183fefb2b9
commit 32cb358c81
3 changed files with 9 additions and 6 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -52,17 +52,17 @@ trait HasRocketTiles extends HasSystemBus
case AsynchronousCrossing(depth, sync) => { case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra)) val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync) wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)(c.name)
wrapper wrapper
} }
case RationalCrossing(direction) => { case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra)) val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
sbus.fromRationalTiles(direction) :=* wrapper.masterNode sbus.fromRationalTiles(direction) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves wrapper.slaveNode :*= pbus.toRationalSlaves(c.name)
wrapper wrapper
} }
} }
wrapper.suggestName("tile") // Try to stabilize this name for downstream tools c.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
// Local Interrupts must be synchronized to the core clock // Local Interrupts must be synchronized to the core clock
// before being passed into this module. // before being passed into this module.

3
src/main/scala/tile/RocketTile.scala
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@ -18,7 +18,8 @@ case class RocketTileParams(
rocc: Seq[RoCCParams] = Nil, rocc: Seq[RoCCParams] = Nil,
btb: Option[BTBParams] = Some(BTBParams()), btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0, dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false) extends TileParams { boundaryBuffers: Boolean = false,
name: Option[String] = Some("tile")) extends TileParams {
require(icache.isDefined) require(icache.isDefined)
require(dcache.isDefined) require(dcache.isDefined)
} }

6
src/main/scala/tilelink/Bus.scala
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@ -63,14 +63,16 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
def bufferToSlaves: TLOutwardNode = outwardBufNode def bufferToSlaves: TLOutwardNode = outwardBufNode
def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = { def toAsyncSlaves(sync: Int = 3)(name: Option[String] = None): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync)) val source = LazyModule(new TLAsyncCrossingSource(sync))
name.foreach(source.suggestName)
source.node :*= outwardNode source.node :*= outwardNode
source.node source.node
} }
def toRationalSlaves: TLRationalOutwardNode = { def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
val source = LazyModule(new TLRationalCrossingSource()) val source = LazyModule(new TLRationalCrossingSource())
name.foreach(source.suggestName)
source.node :*= outwardNode source.node :*= outwardNode
source.node source.node
} }