From 32cb358c81d9cf32e67b3cf21cd400cf71141e7d Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 30 Aug 2017 15:23:10 -0700
Subject: [PATCH] coreplex: include optional tile name for downstream name
 stabilization

---
 src/main/scala/coreplex/RocketCoreplex.scala | 6 +++---
 src/main/scala/tile/RocketTile.scala         | 3 ++-
 src/main/scala/tilelink/Bus.scala            | 6 ++++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index a30cdad5..11d64887 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -52,17 +52,17 @@ trait HasRocketTiles extends HasSystemBus
       case AsynchronousCrossing(depth, sync) => {
         val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
         sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)
+        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)(c.name)
         wrapper
       }
       case RationalCrossing(direction) => {
         val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
         sbus.fromRationalTiles(direction) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toRationalSlaves
+        wrapper.slaveNode :*= pbus.toRationalSlaves(c.name)
         wrapper
       }
     }
-    wrapper.suggestName("tile") // Try to stabilize this name for downstream tools
+    c.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
 
     // Local Interrupts must be synchronized to the core clock
     // before being passed into this module.
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 3490b6c9..88541bff 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -18,7 +18,8 @@ case class RocketTileParams(
     rocc: Seq[RoCCParams] = Nil,
     btb: Option[BTBParams] = Some(BTBParams()),
     dataScratchpadBytes: Int = 0,
-    boundaryBuffers: Boolean = false) extends TileParams {
+    boundaryBuffers: Boolean = false,
+    name: Option[String] = Some("tile")) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 9d72ad7c..612b8cdd 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -63,14 +63,16 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode 
 
-  def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+  def toAsyncSlaves(sync: Int = 3)(name: Option[String] = None): TLAsyncOutwardNode = {
     val source = LazyModule(new TLAsyncCrossingSource(sync))
+    name.foreach(source.suggestName)
     source.node :*= outwardNode
     source.node
   }
 
-  def toRationalSlaves: TLRationalOutwardNode = {
+  def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
     val source = LazyModule(new TLRationalCrossingSource())
+    name.foreach(source.suggestName)
     source.node :*= outwardNode
     source.node
   }