From 3209e588458308d0dfc46a5fd358b5b19e4f9521 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 8 May 2017 00:30:40 -0700 Subject: [PATCH] axi4: SRAM support 0 userBits --- src/main/scala/uncore/axi4/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/axi4/SRAM.scala b/src/main/scala/uncore/axi4/SRAM.scala index e0ae971b..6c53cc02 100644 --- a/src/main/scala/uncore/axi4/SRAM.scala +++ b/src/main/scala/uncore/axi4/SRAM.scala @@ -40,7 +40,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = val w_full = RegInit(Bool(false)) val w_id = Reg(UInt()) - val w_user = Reg(UInt()) + val w_user = Reg(UInt(width = 1 max in.params.userBits)) when (in. b.fire()) { w_full := Bool(false) } when (in.aw.fire()) { w_full := Bool(true) } @@ -65,7 +65,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = val r_full = RegInit(Bool(false)) val r_id = Reg(UInt()) - val r_user = Reg(UInt()) + val r_user = Reg(UInt(width = 1 max in.params.userBits)) when (in. r.fire()) { r_full := Bool(false) } when (in.ar.fire()) { r_full := Bool(true) }