riscv/rocket-chip
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coreplex: buses are now LazyModules with LazyScope

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This commit is contained in:
Wesley W. Terpstra 2017-09-26 14:58:18 -07:00
parent da40573a64
commit 31a934bec0
5 changed files with 6 additions and 5 deletions
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2
src/main/scala/coreplex/FrontBus.scala
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@ -53,7 +53,7 @@ trait HasFrontBus extends HasSystemBus {
private val frontbusParams = p(FrontBusKey) private val frontbusParams = p(FrontBusKey)
val frontbusBeatBytes = frontbusParams.beatBytes val frontbusBeatBytes = frontbusParams.beatBytes
val fbus = new FrontBus(frontbusParams) val fbus = LazyModule(new FrontBus(frontbusParams))
sbus.fromFrontBus := fbus.toSystemBus sbus.fromFrontBus := fbus.toSystemBus

2
src/main/scala/coreplex/MemoryBus.scala
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@ -66,7 +66,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
private val (in, out) = coherenceManager(p, this) private val (in, out) = coherenceManager(p, this)
private val mask = ~BigInt((nBanks-1) * blockBytes) private val mask = ~BigInt((nBanks-1) * blockBytes)
val memBuses = Seq.tabulate(nMemoryChannels) { channel => val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
val mbus = new MemoryBus(mbusParams) val mbus = LazyModule(new MemoryBus(mbusParams))
for (bank <- 0 until nBanksPerChannel) { for (bank <- 0 until nBanksPerChannel) {
val offset = (bank * nMemoryChannels) + channel val offset = (bank * nMemoryChannels) + channel
ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus } ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }

2
src/main/scala/coreplex/PeripheryBus.scala
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@ -45,7 +45,7 @@ trait HasPeripheryBus extends HasSystemBus {
private val pbusParams = p(PeripheryBusKey) private val pbusParams = p(PeripheryBusKey)
val pbusBeatBytes = pbusParams.beatBytes val pbusBeatBytes = pbusParams.beatBytes
val pbus = new PeripheryBus(pbusParams) val pbus = LazyModule(new PeripheryBus(pbusParams))
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus := sbus.toPeripheryBus() pbus.fromSystemBus := sbus.toPeripheryBus()

2
src/main/scala/coreplex/SystemBus.scala
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@ -122,7 +122,7 @@ trait HasSystemBus extends HasInterruptBus {
private val sbusParams = p(SystemBusKey) private val sbusParams = p(SystemBusKey)
val sbusBeatBytes = sbusParams.beatBytes val sbusBeatBytes = sbusParams.beatBytes
val sbus = new SystemBus(sbusParams) val sbus = LazyModule(new SystemBus(sbusParams))
def sharedMemoryTLEdge: TLEdge = sbus.busView def sharedMemoryTLEdge: TLEdge = sbus.busView
def paddrBits: Int = sbus.busView.bundle.addressBits def paddrBits: Int = sbus.busView.bundle.addressBits

3
src/main/scala/tilelink/Bus.scala
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@ -21,7 +21,8 @@ trait TLBusParams {
def blockOffset: Int = log2Up(blockBytes) def blockOffset: Int = log2Up(blockBytes)
} }
abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams { abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters)
extends SimpleLazyModule with LazyScope with TLBusParams {
val beatBytes = params.beatBytes val beatBytes = params.beatBytes
val blockBytes = params.blockBytes val blockBytes = params.blockBytes