From 31a934bec08124c3aa91706cb812e100d6ded837 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 26 Sep 2017 14:58:18 -0700
Subject: [PATCH] coreplex: buses are now LazyModules with LazyScope

---
 src/main/scala/coreplex/FrontBus.scala     | 2 +-
 src/main/scala/coreplex/MemoryBus.scala    | 2 +-
 src/main/scala/coreplex/PeripheryBus.scala | 2 +-
 src/main/scala/coreplex/SystemBus.scala    | 2 +-
 src/main/scala/tilelink/Bus.scala          | 3 ++-
 5 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 60be007e..98d080bc 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -53,7 +53,7 @@ trait HasFrontBus extends HasSystemBus {
   private val frontbusParams = p(FrontBusKey)
   val frontbusBeatBytes = frontbusParams.beatBytes
 
-  val fbus = new FrontBus(frontbusParams)
+  val fbus = LazyModule(new FrontBus(frontbusParams))
 
   sbus.fromFrontBus := fbus.toSystemBus
 
diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala
index 4127426a..879a08e9 100644
--- a/src/main/scala/coreplex/MemoryBus.scala
+++ b/src/main/scala/coreplex/MemoryBus.scala
@@ -66,7 +66,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
   private val (in, out) = coherenceManager(p, this)
   private val mask = ~BigInt((nBanks-1) * blockBytes)
   val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
-    val mbus = new MemoryBus(mbusParams)
+    val mbus = LazyModule(new MemoryBus(mbusParams))
     for (bank <- 0 until nBanksPerChannel) {
       val offset = (bank * nMemoryChannels) + channel
       ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 1de255ed..3272a3b1 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -45,7 +45,7 @@ trait HasPeripheryBus extends HasSystemBus {
   private val pbusParams = p(PeripheryBusKey)
   val pbusBeatBytes = pbusParams.beatBytes
 
-  val pbus = new PeripheryBus(pbusParams)
+  val pbus = LazyModule(new PeripheryBus(pbusParams))
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
   pbus.fromSystemBus := sbus.toPeripheryBus()
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 384da306..6721ead8 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -122,7 +122,7 @@ trait HasSystemBus extends HasInterruptBus {
   private val sbusParams = p(SystemBusKey)
   val sbusBeatBytes = sbusParams.beatBytes
 
-  val sbus = new SystemBus(sbusParams)
+  val sbus = LazyModule(new SystemBus(sbusParams))
 
   def sharedMemoryTLEdge: TLEdge = sbus.busView
   def paddrBits: Int = sbus.busView.bundle.addressBits
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 4abbf5ab..5f2d018b 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -21,7 +21,8 @@ trait TLBusParams {
   def blockOffset: Int = log2Up(blockBytes)
 }
 
-abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams {
+abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters)
+    extends SimpleLazyModule with LazyScope with TLBusParams {
 
   val beatBytes = params.beatBytes
   val blockBytes = params.blockBytes