coreplex: buses are now LazyModules with LazyScope
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da40573a64
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@ -53,7 +53,7 @@ trait HasFrontBus extends HasSystemBus {
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private val frontbusParams = p(FrontBusKey)
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private val frontbusParams = p(FrontBusKey)
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val frontbusBeatBytes = frontbusParams.beatBytes
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val frontbusBeatBytes = frontbusParams.beatBytes
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val fbus = new FrontBus(frontbusParams)
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val fbus = LazyModule(new FrontBus(frontbusParams))
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sbus.fromFrontBus := fbus.toSystemBus
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sbus.fromFrontBus := fbus.toSystemBus
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@ -66,7 +66,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
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private val (in, out) = coherenceManager(p, this)
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private val (in, out) = coherenceManager(p, this)
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private val mask = ~BigInt((nBanks-1) * blockBytes)
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private val mask = ~BigInt((nBanks-1) * blockBytes)
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val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
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val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
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val mbus = new MemoryBus(mbusParams)
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val mbus = LazyModule(new MemoryBus(mbusParams))
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for (bank <- 0 until nBanksPerChannel) {
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for (bank <- 0 until nBanksPerChannel) {
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val offset = (bank * nMemoryChannels) + channel
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val offset = (bank * nMemoryChannels) + channel
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ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
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ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
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@ -45,7 +45,7 @@ trait HasPeripheryBus extends HasSystemBus {
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private val pbusParams = p(PeripheryBusKey)
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private val pbusParams = p(PeripheryBusKey)
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val pbusBeatBytes = pbusParams.beatBytes
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val pbusBeatBytes = pbusParams.beatBytes
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val pbus = new PeripheryBus(pbusParams)
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val pbus = LazyModule(new PeripheryBus(pbusParams))
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// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus := sbus.toPeripheryBus()
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pbus.fromSystemBus := sbus.toPeripheryBus()
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@ -122,7 +122,7 @@ trait HasSystemBus extends HasInterruptBus {
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private val sbusParams = p(SystemBusKey)
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private val sbusParams = p(SystemBusKey)
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val sbusBeatBytes = sbusParams.beatBytes
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val sbusBeatBytes = sbusParams.beatBytes
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val sbus = new SystemBus(sbusParams)
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val sbus = LazyModule(new SystemBus(sbusParams))
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def sharedMemoryTLEdge: TLEdge = sbus.busView
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def sharedMemoryTLEdge: TLEdge = sbus.busView
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def paddrBits: Int = sbus.busView.bundle.addressBits
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def paddrBits: Int = sbus.busView.bundle.addressBits
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@ -21,7 +21,8 @@ trait TLBusParams {
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def blockOffset: Int = log2Up(blockBytes)
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def blockOffset: Int = log2Up(blockBytes)
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}
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}
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abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams {
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abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters)
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extends SimpleLazyModule with LazyScope with TLBusParams {
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val beatBytes = params.beatBytes
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val beatBytes = params.beatBytes
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val blockBytes = params.blockBytes
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val blockBytes = params.blockBytes
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