riscv/rocket-chip
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coreplex: buses are now LazyModules with LazyScope

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Wesley W. Terpstra committed 2017-09-26 14:58:56 -07:00
1 parent da40573a64
commit 31a934bec0
5 files changed
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src/main/scala/coreplex/SystemBus.scala
+1 -1
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@@ -122,7 +122,7 @@ trait HasSystemBus extends HasInterruptBus {
private val sbusParams = p(SystemBusKey)
val sbusBeatBytes = sbusParams.beatBytes
val sbus = new SystemBus(sbusParams)
val sbus = LazyModule(new SystemBus(sbusParams))
def sharedMemoryTLEdge: TLEdge = sbus.busView
def paddrBits: Int = sbus.busView.bundle.addressBits