remove second RF write port
load miss writebacks are treated like mul/div now.
This commit is contained in:
parent
ffe23a1ee8
commit
3045b33460
@ -101,9 +101,11 @@ class rocketProc extends Component
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arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
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ctrl.io.dmem.req_rdy := dtlb.io.cpu.req_rdy && arb.io.cpu.req_rdy;
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ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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ctrl.io.dmem.resp_replay:= arb.io.cpu.resp_replay;
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ctrl.io.dmem.resp_nack := arb.io.cpu.resp_nack;
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dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
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dpath.io.dmem.resp_replay := io.dmem.resp_replay;
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dpath.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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dpath.io.dmem.resp_replay := arb.io.cpu.resp_replay;
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dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
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dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
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dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;
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@ -64,10 +64,8 @@ class ioCtrlDpath extends Bundle()
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val mem_waddr = UFix(5,'input); // write addr from memory stage
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val wb_waddr = UFix(5,'input); // write addr from writeback stage
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val status = Bits(17, 'input);
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val sboard_clr0 = Bool('input);
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val sboard_clr0a = UFix(5, 'input);
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val sboard_clr1 = Bool('input);
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val sboard_clr1a = UFix(5, 'input);
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val sboard_clr = Bool('input);
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val sboard_clra = UFix(5, 'input);
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val mem_valid = Bool('input); // high if there's a valid (not flushed) instruction in mem stage
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val irq_timer = Bool('input);
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val irq_ipi = Bool('input);
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@ -78,7 +76,7 @@ class ioCtrlAll extends Bundle()
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val dpath = new ioCtrlDpath();
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val console = new ioConsole(List("rdy"));
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val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
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val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
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val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
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val host = new ioHost(List("start"));
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val dtlb_val = Bool('output)
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val dtlb_rdy = Bool('input);
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@ -186,26 +184,26 @@ class rocketCtrl extends Component
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JALR_R-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LW-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LD-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LBU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LHU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LWU-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LW-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LD-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LBU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LHU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LWU-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SB-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SH-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SW-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SD-> List(xpr64, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOADD_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOSWAP_W->List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOAND_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOOR_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOADD_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOSWAP_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOAND_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOOR_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOADD_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOSWAP_W->List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOAND_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOOR_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOADD_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOSWAP_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOAND_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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AMOOR_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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LUI-> List(Y, BR_N, REN_N,REN_Y,A2_0, A1_LUI,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SLTI -> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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@ -318,10 +316,8 @@ class rocketCtrl extends Component
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sboard.io.set := wb_reg_div_mul_val | dcache_miss;
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sboard.io.seta := io.dpath.wb_waddr;
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sboard.io.clr0 := io.dpath.sboard_clr0;
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sboard.io.clr0a := io.dpath.sboard_clr0a;
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sboard.io.clr1 := io.dpath.sboard_clr1;
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sboard.io.clr1a := io.dpath.sboard_clr1a;
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sboard.io.clr := io.dpath.sboard_clr;
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sboard.io.clra := io.dpath.sboard_clra;
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val id_stall_raddr2 = sboard.io.stalla;
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val id_stall_raddr1 = sboard.io.stallb;
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@ -614,6 +610,11 @@ class rocketCtrl extends Component
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val data_hazard = data_hazard_ex || data_hazard_mem || data_hazard_wb;
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// for divider, multiplier, load miss writeback
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val mem_wb = Reg(io.dmem.resp_replay, resetVal = Bool(false)) // delayed for subword extension
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val mul_wb = io.dpath.mul_result_val && !io.dmem.resp_replay;
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val div_wb = io.dpath.div_result_val && !io.dpath.mul_result_val && !io.dmem.resp_replay;
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val ctrl_stalld =
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!take_pc &&
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(
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@ -627,16 +628,13 @@ class rocketCtrl extends Component
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id_div_val.toBool && !io.dpath.div_rdy ||
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id_mul_val.toBool && !io.dpath.mul_rdy ||
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io.dpath.div_result_val ||
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io.dpath.mul_result_val
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io.dpath.mul_result_val ||
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mem_wb
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);
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val ctrl_killd = take_pc || ctrl_stalld;
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val ctrl_killf = take_pc || !io.imem.resp_val;
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// for divider, multiplier writeback
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val mul_wb = io.dpath.mul_result_val;
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val div_wb = io.dpath.div_result_val & !mul_wb;
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io.flush_inst := mem_reg_flush_inst;
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io.dpath.stalld := ctrl_stalld;
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@ -6,10 +6,8 @@ import Constants._;
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class ioCtrlSboard extends Bundle()
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{
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val clr0 = Bool('input);
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val clr0a = UFix(5, 'input);
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val clr1 = Bool('input);
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val clr1a = UFix(5, 'input);
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val clr = Bool('input);
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val clra = UFix(5, 'input);
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val set = Bool('input);
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val seta = UFix(5, 'input);
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val raddra = UFix(5, 'input);
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@ -25,10 +23,9 @@ class rocketCtrlSboard extends Component
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override val io = new ioCtrlSboard();
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val reg_busy = Reg(width = 32, resetVal = Bits(0, 32));
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val set_mask = Mux(io.set, UFix(1,1) << io.seta, UFix(0,32));
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val clr0_mask = Mux(io.clr0, ~(UFix(1,1) << io.clr0a), ~UFix(0,32));
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val clr1_mask = Mux(io.clr1, ~(UFix(1,1) << io.clr1a), ~UFix(0,32));
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reg_busy <== ((reg_busy | set_mask) & clr0_mask) & clr1_mask;
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val set_mask = io.set.toUFix << io.seta;
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val clr_mask = ~(io.clr.toUFix << io.clra);
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reg_busy <== (reg_busy | set_mask) & clr_mask
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io.stalla := reg_busy(io.raddra).toBool;
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io.stallb := reg_busy(io.raddrb).toBool;
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@ -11,6 +11,7 @@ class ioDpathDmem extends Bundle()
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val req_tag = UFix(CPU_TAG_BITS, 'output);
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val req_data = Bits(64, 'output);
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val resp_val = Bool('input);
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val resp_miss = Bool('input);
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val resp_replay = Bool('input);
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val resp_tag = Bits(CPU_TAG_BITS, 'input);
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val resp_data = Bits(64, 'input);
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@ -78,7 +79,6 @@ class rocketDpath extends Component
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val ex_reg_pc_plus4 = Reg() { UFix() };
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val ex_reg_inst = Reg() { Bits() };
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val ex_reg_raddr2 = Reg() { UFix() };
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val ex_reg_raddr1 = Reg() { UFix() };
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val ex_reg_rs2 = Reg() { Bits() };
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val ex_reg_rs1 = Reg() { Bits() };
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val ex_reg_waddr = Reg() { UFix() };
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@ -115,6 +115,7 @@ class rocketDpath extends Component
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val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val r_dmem_resp_val = Reg(resetVal = Bool(false));
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val r_dmem_resp_replay = Reg(resetVal = Bool(false));
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val r_dmem_resp_waddr = Reg() { UFix() };
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// instruction fetch stage
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@ -131,7 +132,8 @@ class rocketDpath extends Component
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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btb.io.correct_target := Mux(io.ctrl.ex_jr, ex_jr_target, ex_branch_target);
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val jr_br_target = Mux(io.ctrl.ex_jr, ex_jr_target, ex_branch_target);
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btb.io.correct_target := jr_br_target
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val if_next_pc =
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Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
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@ -158,7 +160,7 @@ class rocketDpath extends Component
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btb.io.hit ^^ io.ctrl.btb_hit;
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btb.io.wen ^^ io.ctrl.wen_btb;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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io.ctrl.btb_match := id_reg_pc === btb.io.correct_target;
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io.ctrl.btb_match := id_reg_pc === jr_br_target;
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// instruction decode stage
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when (!io.ctrl.stalld) {
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@ -187,32 +189,35 @@ class rocketDpath extends Component
|
||||
val id_rdata1 = rfile.io.r1.data;
|
||||
|
||||
// destination register selection
|
||||
val id_ctrl_ll_wb = io.ctrl.div_wb || io.ctrl.mul_wb || r_dmem_resp_replay;
|
||||
val id_waddr =
|
||||
Mux(io.ctrl.div_wb, div_result_tag,
|
||||
Mux(r_dmem_resp_replay, r_dmem_resp_waddr,
|
||||
Mux(io.ctrl.mul_wb, mul_result_tag,
|
||||
Mux(io.ctrl.div_wb, div_result_tag,
|
||||
Mux(io.ctrl.sel_wa === WA_RD, id_reg_inst(31,27).toUFix,
|
||||
Mux(io.ctrl.sel_wa === WA_RA, RA,
|
||||
UFix(0, 5)))));
|
||||
UFix(0, 5))))));
|
||||
|
||||
// bypass muxes
|
||||
val rs1_mem_lu_bypass = id_raddr1 != UFix(0, 5) && io.ctrl.mem_load && id_raddr1 === mem_reg_waddr;
|
||||
val id_rs1 =
|
||||
Mux(r_dmem_resp_replay, io.dmem.resp_data_subword,
|
||||
Mux(io.ctrl.div_wb, div_result,
|
||||
Mux(io.ctrl.mul_wb, mul_result,
|
||||
Mux(id_raddr1 != UFix(0, 5) && ex_reg_ctrl_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
|
||||
Mux(id_raddr1 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
|
||||
Mux(id_raddr1 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
|
||||
Mux(rs1_mem_lu_bypass, io.dmem.resp_data,
|
||||
Mux(id_raddr1 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
|
||||
Mux(id_raddr1 != UFix(0, 5) && r_dmem_resp_val && id_raddr1 === r_dmem_resp_waddr, io.dmem.resp_data_subword,
|
||||
Mux(id_raddr1 != UFix(0, 5) && wb_reg_ctrl_wen && id_raddr1 === wb_reg_waddr, wb_reg_wdata,
|
||||
id_rdata1)))))));
|
||||
Mux(id_raddr1 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_reg_wdata,
|
||||
id_rdata1))))))));
|
||||
|
||||
val rs2_mem_lu_bypass = id_raddr2 != UFix(0, 5) && io.ctrl.mem_load && id_raddr2 === mem_reg_waddr;
|
||||
val id_rs2 =
|
||||
Mux(id_raddr2 != UFix(0, 5) && ex_reg_ctrl_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
|
||||
Mux(id_raddr2 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
|
||||
Mux(id_raddr2 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
|
||||
Mux(rs2_mem_lu_bypass, io.dmem.resp_data,
|
||||
Mux(id_raddr2 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
|
||||
Mux(id_raddr2 != UFix(0, 5) && r_dmem_resp_val && id_raddr2 === r_dmem_resp_waddr, io.dmem.resp_data_subword,
|
||||
Mux(id_raddr2 != UFix(0, 5) && wb_reg_ctrl_wen && id_raddr2 === wb_reg_waddr, wb_reg_wdata,
|
||||
Mux(id_raddr2 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_reg_wdata,
|
||||
id_rdata2)))));
|
||||
|
||||
io.ctrl.mem_lu_bypass := rs1_mem_lu_bypass || rs2_mem_lu_bypass;
|
||||
@ -223,7 +228,6 @@ class rocketDpath extends Component
|
||||
ex_reg_pc_plus4 <== id_reg_pc_plus4;
|
||||
ex_reg_inst <== id_reg_inst;
|
||||
ex_reg_raddr2 <== id_raddr2;
|
||||
ex_reg_raddr1 <== id_raddr1;
|
||||
ex_reg_rs2 <== id_rs2;
|
||||
ex_reg_rs1 <== id_rs1;
|
||||
ex_reg_waddr <== id_waddr;
|
||||
@ -233,7 +237,7 @@ class rocketDpath extends Component
|
||||
ex_reg_ctrl_fn_alu <== io.ctrl.fn_alu;
|
||||
ex_reg_ctrl_mul_fn <== io.ctrl.mul_fn;
|
||||
ex_reg_ctrl_div_fn <== io.ctrl.div_fn;
|
||||
ex_reg_ctrl_ll_wb <== io.ctrl.div_wb | io.ctrl.mul_wb; // TODO: verify
|
||||
ex_reg_ctrl_ll_wb <== id_ctrl_ll_wb;
|
||||
ex_reg_ctrl_sel_wb <== io.ctrl.sel_wb;
|
||||
ex_reg_ctrl_ren_pcr <== io.ctrl.ren_pcr;
|
||||
|
||||
@ -371,6 +375,7 @@ class rocketDpath extends Component
|
||||
|
||||
// writeback stage
|
||||
r_dmem_resp_val <== io.dmem.resp_val;
|
||||
r_dmem_resp_replay <== io.dmem.resp_replay;
|
||||
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix
|
||||
|
||||
wb_reg_waddr <== mem_reg_waddr;
|
||||
@ -381,27 +386,21 @@ class rocketDpath extends Component
|
||||
wb_reg_ctrl_wen <== Bool(false);
|
||||
}
|
||||
otherwise {
|
||||
wb_reg_ctrl_wen <== mem_reg_ctrl_wen;
|
||||
wb_reg_ctrl_wen <== mem_reg_ctrl_wen && !io.dmem.resp_miss;
|
||||
}
|
||||
|
||||
// crossbar/sign extension for 8/16 bit loads (moved to earlier in file)
|
||||
|
||||
// regfile write
|
||||
rfile.io.w0.addr := wb_reg_waddr;
|
||||
rfile.io.w0.en := wb_reg_ctrl_wen | wb_reg_ctrl_ll_wb;
|
||||
rfile.io.w0.data := wb_reg_wdata;
|
||||
|
||||
rfile.io.w1.addr := r_dmem_resp_waddr;
|
||||
rfile.io.w1.en := r_dmem_resp_val;
|
||||
rfile.io.w1.data := io.dmem.resp_data_subword;
|
||||
rfile.io.w0.en := wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb;
|
||||
rfile.io.w0.data := Mux(Reg(io.ctrl.mem_load), io.dmem.resp_data_subword, wb_reg_wdata);
|
||||
|
||||
io.ctrl.wb_waddr := wb_reg_waddr;
|
||||
|
||||
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
||||
io.ctrl.sboard_clr0 := wb_reg_ctrl_ll_wb;
|
||||
io.ctrl.sboard_clr0a := wb_reg_waddr;
|
||||
io.ctrl.sboard_clr1 := r_dmem_resp_val;
|
||||
io.ctrl.sboard_clr1a := r_dmem_resp_waddr;
|
||||
io.ctrl.sboard_clr := id_ctrl_ll_wb;
|
||||
io.ctrl.sboard_clra := id_waddr;
|
||||
|
||||
// processor control regfile write
|
||||
pcr.io.w.addr := mem_reg_raddr2;
|
||||
|
@ -219,14 +219,12 @@ class ioRegfile extends Bundle()
|
||||
val r0 = new ioReadPort();
|
||||
val r1 = new ioReadPort();
|
||||
val w0 = new ioWritePort();
|
||||
val w1 = new ioWritePort();
|
||||
}
|
||||
|
||||
class rocketDpathRegfile extends Component
|
||||
{
|
||||
override val io = new ioRegfile();
|
||||
val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
|
||||
regfile.write(io.w1.en && (io.w1.addr != UFix(0,5)), io.w1.addr, io.w1.data);
|
||||
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
|
||||
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
|
||||
}
|
||||
|
@ -7,7 +7,7 @@ import scala.math._;
|
||||
|
||||
class ioDmemArbiter extends Bundle
|
||||
{
|
||||
val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_nack"));
|
||||
val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_replay", "resp_nack"));
|
||||
val cpu = new ioDmem();
|
||||
val mem = new ioDmem().flip();
|
||||
}
|
||||
@ -40,6 +40,9 @@ class rocketDmemArbiter extends Component
|
||||
io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
|
||||
io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
|
||||
|
||||
io.cpu.resp_replay := io.mem.resp_replay && !io.mem.resp_tag(0).toBool;
|
||||
io.ptw.resp_replay := io.mem.resp_replay && io.mem.resp_tag(0).toBool;
|
||||
|
||||
io.ptw.resp_data := io.mem.resp_data;
|
||||
io.cpu.resp_data := io.mem.resp_data;
|
||||
io.cpu.resp_tag := io.mem.resp_tag >> UFix(1);
|
||||
|
Loading…
Reference in New Issue
Block a user