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remove second RF write port

load miss writebacks are treated like mul/div now.
This commit is contained in:
Andrew Waterman
2012-01-02 02:51:30 -08:00
parent ffe23a1ee8
commit 3045b33460
6 changed files with 63 additions and 66 deletions

View File

@ -7,7 +7,7 @@ import scala.math._;
class ioDmemArbiter extends Bundle
{
val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_nack"));
val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_replay", "resp_nack"));
val cpu = new ioDmem();
val mem = new ioDmem().flip();
}
@ -40,6 +40,9 @@ class rocketDmemArbiter extends Component
io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
io.cpu.resp_replay := io.mem.resp_replay && !io.mem.resp_tag(0).toBool;
io.ptw.resp_replay := io.mem.resp_replay && io.mem.resp_tag(0).toBool;
io.ptw.resp_data := io.mem.resp_data;
io.cpu.resp_data := io.mem.resp_data;
io.cpu.resp_tag := io.mem.resp_tag >> UFix(1);