remove second RF write port
load miss writebacks are treated like mul/div now.
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@ -7,7 +7,7 @@ import scala.math._;
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class ioDmemArbiter extends Bundle
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{
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val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_nack"));
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val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_replay", "resp_nack"));
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val cpu = new ioDmem();
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val mem = new ioDmem().flip();
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}
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@ -40,6 +40,9 @@ class rocketDmemArbiter extends Component
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io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
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io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
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io.cpu.resp_replay := io.mem.resp_replay && !io.mem.resp_tag(0).toBool;
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io.ptw.resp_replay := io.mem.resp_replay && io.mem.resp_tag(0).toBool;
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io.ptw.resp_data := io.mem.resp_data;
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io.cpu.resp_data := io.mem.resp_data;
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io.cpu.resp_tag := io.mem.resp_tag >> UFix(1);
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