riscv/rocket-chip
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remove second RF write port

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load miss writebacks are treated like mul/div now.
This commit is contained in:
Andrew Waterman
2012-01-02 02:51:30 -08:00
parent ffe23a1ee8
commit 3045b33460
6 changed files with 63 additions and 66 deletions
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2
rocket/src/main/scala/dpath_util.scala
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@ -219,14 +219,12 @@ class ioRegfile extends Bundle()
val r0 = new ioReadPort();
val r1 = new ioReadPort();
val w0 = new ioWritePort();
val w1 = new ioWritePort();
}
class rocketDpathRegfile extends Component
{
override val io = new ioRegfile();
val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
regfile.write(io.w1.en && (io.w1.addr != UFix(0,5)), io.w1.addr, io.w1.data);
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
}