riscv/rocket-chip
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remove second RF write port

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load miss writebacks are treated like mul/div now.
This commit is contained in:
Andrew Waterman
2012-01-02 02:51:30 -08:00
parent ffe23a1ee8
commit 3045b33460
6 changed files with 63 additions and 66 deletions
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4
rocket/src/main/scala/cpu.scala
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@ -101,9 +101,11 @@ class rocketProc extends Component
arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.req_rdy := dtlb.io.cpu.req_rdy && arb.io.cpu.req_rdy;
ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
ctrl.io.dmem.resp_replay:= arb.io.cpu.resp_replay;
ctrl.io.dmem.resp_nack := arb.io.cpu.resp_nack;
dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_replay := io.dmem.resp_replay;
dpath.io.dmem.resp_miss := arb.io.cpu.resp_miss;
dpath.io.dmem.resp_replay := arb.io.cpu.resp_replay;
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;