riscv/rocket-chip
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rocket: reverse input edge for better output

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This commit is contained in:
Wesley W. Terpstra
2017-04-14 16:53:40 -07:00
parent ae8fd0c60f
commit 2f22fca615
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/rocket/Tile.scala
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@@ -160,7 +160,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
val masterNode = TLOutputNode() val masterNode = TLOutputNode()
masterNode :=* rocket.masterNode masterNode :=* rocket.masterNode
val slaveNode = TLInputNode() val slaveNode = new TLInputNode() { override def reverse = true }
rocket.slaveNode :*= slaveNode rocket.slaveNode :*= slaveNode
val intNode = IntInputNode() val intNode = IntInputNode()
@@ -194,7 +194,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
source.node :=* rocket.masterNode source.node :=* rocket.masterNode
masterNode :=* source.node masterNode :=* source.node
val slaveNode = TLAsyncInputNode() val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink) val sink = LazyModule(new TLAsyncCrossingSink)
rocket.slaveNode :*= sink.node rocket.slaveNode :*= sink.node
sink.node :*= slaveNode sink.node :*= slaveNode
@@ -226,7 +226,7 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
source.node :=* rocket.masterNode source.node :=* rocket.masterNode
masterNode :=* source.node masterNode :=* source.node
val slaveNode = TLRationalInputNode() val slaveNode = new TLRationalInputNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(util.SlowToFast)) val sink = LazyModule(new TLRationalCrossingSink(util.SlowToFast))
rocket.slaveNode :*= sink.node rocket.slaveNode :*= sink.node
sink.node :*= slaveNode sink.node :*= slaveNode