From 2f22fca61531ed08c65f98362df0b65328747256 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 14 Apr 2017 16:53:40 -0700
Subject: [PATCH] rocket: reverse input edge for better output

---
 src/main/scala/rocket/Tile.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/Tile.scala
index bec3190c..eef8f5a1 100644
--- a/src/main/scala/rocket/Tile.scala
+++ b/src/main/scala/rocket/Tile.scala
@@ -160,7 +160,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
   val masterNode = TLOutputNode()
   masterNode :=* rocket.masterNode
 
-  val slaveNode = TLInputNode()
+  val slaveNode = new TLInputNode() { override def reverse = true }
   rocket.slaveNode :*= slaveNode
 
   val intNode = IntInputNode()
@@ -194,7 +194,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
   source.node :=* rocket.masterNode
   masterNode :=* source.node
 
-  val slaveNode = TLAsyncInputNode()
+  val slaveNode = new TLAsyncInputNode() { override def reverse = true }
   val sink = LazyModule(new TLAsyncCrossingSink)
   rocket.slaveNode :*= sink.node
   sink.node :*= slaveNode
@@ -226,7 +226,7 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
   source.node :=* rocket.masterNode
   masterNode :=* source.node
 
-  val slaveNode = TLRationalInputNode()
+  val slaveNode = new TLRationalInputNode() { override def reverse = true }
   val sink = LazyModule(new TLRationalCrossingSink(util.SlowToFast))
   rocket.slaveNode :*= sink.node
   sink.node :*= slaveNode