Added functional covers
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@ -5,6 +5,8 @@ package freechips.rocketchip.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import scala.math.max
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import scala.math.max
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class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
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class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
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@ -98,6 +100,31 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
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out.c.valid := Bool(false)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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//Functional cover properties
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cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
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val SourceIdFIFOed = RegInit(UInt(0, width = edgeIn.client.endSourceId))
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val SourceIdSet = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
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val SourceIdClear = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
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when (a_first && in.a.fire() && !a_notFIFO) {
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SourceIdSet := UIntToOH(in.a.bits.source)
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}
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when (d_first && in.d.fire()) {
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SourceIdClear := UIntToOH(in.d.bits.source)
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}
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SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
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val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
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cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
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//cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
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cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
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cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
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cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
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}
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}
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}
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}
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}
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}
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