diff --git a/src/main/scala/tilelink/FIFOFixer.scala b/src/main/scala/tilelink/FIFOFixer.scala
index bd3adab2..2e992c3f 100644
--- a/src/main/scala/tilelink/FIFOFixer.scala
+++ b/src/main/scala/tilelink/FIFOFixer.scala
@@ -5,6 +5,8 @@ package freechips.rocketchip.tilelink
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util._
+import freechips.rocketchip.util.property._
 import scala.math.max
 
 class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
@@ -98,6 +100,31 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
         out.c.valid := Bool(false)
         out.e.valid := Bool(false)
       }
+
+//Functional cover properties
+     
+      cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
+
+      val SourceIdFIFOed = RegInit(UInt(0, width = edgeIn.client.endSourceId))
+      val SourceIdSet = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
+      val SourceIdClear = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
+
+      when (a_first && in.a.fire() && !a_notFIFO)  {
+        SourceIdSet := UIntToOH(in.a.bits.source)
+      }
+      when (d_first && in.d.fire())  {
+        SourceIdClear := UIntToOH(in.d.bits.source)
+      }
+
+      SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
+      val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
+
+      cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
+    //cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
+      cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
+      cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
+      cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
+
     }
   }
 }