Fix RV64 badaddr value on instruction faults with large addresses
We were relying on ALU passthrough for this, but failed to override the ALU dw argument, so bits above 31 could be discarded.
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@ -55,7 +55,7 @@ trait ScalarOpConstants {
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val SZ_DW = 1
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val DW_X = X
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val DW_32 = N
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val DW_64 = Y
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val DW_XPR = Y
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val DW_32 = Bool(false)
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val DW_64 = Bool(true)
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val DW_XPR = DW_64
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}
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@ -322,6 +322,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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ex_ctrl.csr := id_csr
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when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
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ex_ctrl.alu_fn := ALU.FN_ADD
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ex_ctrl.alu_dw := DW_XPR
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ex_ctrl.sel_alu1 := A1_PC
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ex_ctrl.sel_alu2 := A2_ZERO
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when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2
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