diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 421f9f47..bff13126 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -55,7 +55,7 @@ trait ScalarOpConstants {
 
   val SZ_DW = 1
   val DW_X  = X
-  val DW_32 = N
-  val DW_64 = Y
-  val DW_XPR = Y
+  val DW_32 = Bool(false)
+  val DW_64 = Bool(true)
+  val DW_XPR = DW_64
 }
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 6c3f6e75..34e25454 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -322,6 +322,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
     ex_ctrl.csr := id_csr
     when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
       ex_ctrl.alu_fn := ALU.FN_ADD
+      ex_ctrl.alu_dw := DW_XPR
       ex_ctrl.sel_alu1 := A1_PC
       ex_ctrl.sel_alu2 := A2_ZERO
       when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2