riscv/rocket-chip
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Fix RV64 badaddr value on instruction faults with large addresses

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We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
This commit is contained in:
Andrew Waterman 2016-08-15 17:34:56 -07:00
parent 38e0967816
commit 2d1d7266f5
2 changed files with 4 additions and 3 deletions
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6
rocket/src/main/scala/consts.scala
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@ -55,7 +55,7 @@ trait ScalarOpConstants {
val SZ_DW = 1 val SZ_DW = 1
val DW_X = X val DW_X = X
val DW_32 = N val DW_32 = Bool(false)
val DW_64 = Y val DW_64 = Bool(true)
val DW_XPR = Y val DW_XPR = DW_64
} }

1
rocket/src/main/scala/rocket.scala
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@ -322,6 +322,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
ex_ctrl.csr := id_csr ex_ctrl.csr := id_csr
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := ALU.FN_ADD ex_ctrl.alu_fn := ALU.FN_ADD
ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_ZERO ex_ctrl.sel_alu2 := A2_ZERO
when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2 when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2