diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 7dec9a09..a0d2589b 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -82,6 +82,7 @@ class CSRFileIO extends CoreBundle {
 
   val csr_replay = Bool(OUTPUT)
   val csr_xcpt = Bool(OUTPUT)
+  val eret = Bool(OUTPUT)
 
   val status = new MStatus().asOutput
   val ptbr = UInt(OUTPUT, paddrBits)
@@ -206,7 +207,8 @@ class CSRFile extends CoreModule
              Mux(insn_redirect_trap, reg_stvec,
              Mux(reg_mstatus.prv(1), reg_mepc, reg_sepc))).toUInt
   io.ptbr := reg_sptbr
-  io.csr_xcpt := csr_xcpt || insn_redirect_trap || insn_ret /* sort of a lie */
+  io.csr_xcpt := csr_xcpt
+  io.eret := insn_ret || insn_redirect_trap
   io.status := reg_mstatus
   io.status.fs := reg_mstatus.fs.orR.toSInt // either off or dirty (no clean/initial support yet)
   io.status.xs := reg_mstatus.xs.orR.toSInt // either off or dirty (no clean/initial support yet)
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 450a8817..14cff632 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -45,6 +45,7 @@ class CtrlDpathIO extends CoreBundle
   // inputs from csr file
   val csr_replay = Bool(INPUT)
   val csr_xcpt = Bool(INPUT)
+  val eret = Bool(INPUT)
   val interrupt = Bool(INPUT)
   val interrupt_cause = UInt(INPUT, xLen)
 }
@@ -541,10 +542,10 @@ class Control extends CoreModule
   val wb_xcpt = wb_reg_xcpt || io.dpath.csr_xcpt
 
   // control transfer from ex/wb
-  take_pc_wb := replay_wb || wb_xcpt
+  take_pc_wb := replay_wb || wb_xcpt || io.dpath.eret
 
   io.dpath.sel_pc :=
-    Mux(wb_xcpt,                      PC_PCR, // exception or [m|s]ret
+    Mux(wb_xcpt || io.dpath.eret,     PC_PCR, // exception or [m|s]ret
     Mux(replay_wb,                    PC_WB,  // replay
                                       PC_MEM))