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Discover D$, PTW port counts dynamically

This is a generator, after all...
This commit is contained in:
Andrew Waterman 2016-03-25 14:16:56 -07:00
parent 8d1ba4d1ec
commit 27b3cca046

View File

@ -24,8 +24,6 @@ abstract class Tile(resetSignal: Bool = null)
val usingRocc = !buildRocc.isEmpty val usingRocc = !buildRocc.isEmpty
val nRocc = buildRocc.size val nRocc = buildRocc.size
val nFPUPorts = buildRocc.filter(_.useFPU).size val nFPUPorts = buildRocc.filter(_.useFPU).size
val nDCachePorts = 2 + nRocc
val nPTWPorts = 2 + p(RoccNPTWPorts)
val nCachedTileLinkPorts = 1 val nCachedTileLinkPorts = 1
val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels) val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels)
val dcacheParams = p.alterPartial({ case CacheName => "L1D" }) val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
@ -43,32 +41,20 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
case CacheName => "L1I" case CacheName => "L1I"
case CoreName => "Rocket" }))) case CoreName => "Rocket" })))
val dcache = Module(new HellaCache()(dcacheParams)) val dcache = Module(new HellaCache()(dcacheParams))
val ptw = Module(new PTW(nPTWPorts)(dcacheParams))
val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.io.ptw)
val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
val dcArb = Module(new HellaCacheArbiter(nDCachePorts)(dcacheParams))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem
dcache.io.cpu <> dcArb.io.mem
ptw.io.requestor(0) <> icache.io.ptw
ptw.io.requestor(1) <> dcache.io.ptw
io.host <> core.io.host io.host <> core.io.host
icache.io.cpu <> core.io.imem icache.io.cpu <> core.io.imem
core.io.ptw <> ptw.io.dpath
val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
fpuOpt.foreach(fpu => core.io.fpu <> fpu.io) fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
// Connect the caches and ROCC to the outer memory system if (usingRocc) {
io.cached.head <> dcache.io.mem
// If so specified, build an RoCC module and wire it to core + TileLink ports,
// otherwise just hookup the icache
io.uncached <> (if (usingRocc) {
val uncachedArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
uncachedArb.io.in(0) <> icache.io.mem
val respArb = Module(new RRArbiter(new RoCCResponse, nRocc)) val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
core.io.rocc.resp <> respArb.io.out core.io.rocc.resp <> respArb.io.out
@ -88,8 +74,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
rocc.io.exception := core.io.rocc.exception rocc.io.exception := core.io.rocc.exception
rocc.io.host_id := io.host.id rocc.io.host_id := io.host.id
dcIF.io.requestor <> rocc.io.mem dcIF.io.requestor <> rocc.io.mem
dcArb.io.requestor(2 + i) <> dcIF.io.cache dcPorts += dcIF.io.cache
uncachedArb.io.in(1 + i) <> rocc.io.autl uncachedArbPorts += rocc.io.autl
rocc rocc
} }
@ -108,8 +94,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
} }
} }
ptw.io.requestor.drop(2) <> roccs.flatMap(_.io.ptw)
core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _) core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _) core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp)) respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
@ -126,8 +110,29 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
} }
} }
roccs.flatMap(_.io.utl) :+ uncachedArb.io.out ptwPorts ++= roccs.flatMap(_.io.ptw)
} else { Seq(icache.io.mem) }) uncachedPorts ++= roccs.flatMap(_.io.utl)
}
val uncachedArb = Module(new ClientTileLinkIOArbiter(uncachedArbPorts.size))
uncachedArb.io.in <> uncachedArbPorts
uncachedArb.io.out +=: uncachedPorts
// Connect the caches and RoCC to the outer memory system
io.uncached <> uncachedPorts
io.cached <> cachedPorts
// TODO remove nCached/nUncachedTileLinkPorts parameters and these assertions
require(uncachedPorts.size == nUncachedTileLinkPorts)
require(cachedPorts.size == nCachedTileLinkPorts)
val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
ptw.io.requestor <> ptwPorts
ptw.io.mem +=: dcPorts
core.io.ptw <> ptw.io.dpath
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
dcArb.io.requestor <> dcPorts
dcache.io.cpu <> dcArb.io.mem
if (!usingRocc || nFPUPorts == 0) { if (!usingRocc || nFPUPorts == 0) {
fpuOpt.foreach { fpu => fpuOpt.foreach { fpu =>