From 27b3cca0461bebb8fe68d644aeb973ab5c808ab9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 25 Mar 2016 14:16:56 -0700
Subject: [PATCH] Discover D$, PTW port counts dynamically

This is a generator, after all...
---
 rocket/src/main/scala/tile.scala | 57 +++++++++++++++++---------------
 1 file changed, 31 insertions(+), 26 deletions(-)

diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 4dbda975..1c5926ac 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -24,8 +24,6 @@ abstract class Tile(resetSignal: Bool = null)
   val usingRocc = !buildRocc.isEmpty
   val nRocc = buildRocc.size
   val nFPUPorts = buildRocc.filter(_.useFPU).size
-  val nDCachePorts = 2 + nRocc
-  val nPTWPorts = 2 + p(RoccNPTWPorts)
   val nCachedTileLinkPorts = 1
   val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels)
   val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
@@ -43,32 +41,20 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
     case CacheName => "L1I"
     case CoreName => "Rocket" })))
   val dcache = Module(new HellaCache()(dcacheParams))
-  val ptw = Module(new PTW(nPTWPorts)(dcacheParams))
 
+  val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.io.ptw)
+  val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
+  val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
+  val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
+  val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
   dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
-  val dcArb = Module(new HellaCacheArbiter(nDCachePorts)(dcacheParams))
-  dcArb.io.requestor(0) <> ptw.io.mem
-  dcArb.io.requestor(1) <> core.io.dmem
-  dcache.io.cpu <> dcArb.io.mem
-
-  ptw.io.requestor(0) <> icache.io.ptw
-  ptw.io.requestor(1) <> dcache.io.ptw
-
   io.host <> core.io.host
   icache.io.cpu <> core.io.imem
-  core.io.ptw <> ptw.io.dpath
 
   val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
   fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
 
-   // Connect the caches and ROCC to the outer memory system
-  io.cached.head <> dcache.io.mem
-  // If so specified, build an RoCC module and wire it to core + TileLink ports,
-  // otherwise just hookup the icache
-  io.uncached <> (if (usingRocc) {
-    val uncachedArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
-    uncachedArb.io.in(0) <> icache.io.mem
-
+  if (usingRocc) {
     val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
     core.io.rocc.resp <> respArb.io.out
 
@@ -88,8 +74,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       rocc.io.exception := core.io.rocc.exception
       rocc.io.host_id := io.host.id
       dcIF.io.requestor <> rocc.io.mem
-      dcArb.io.requestor(2 + i) <> dcIF.io.cache
-      uncachedArb.io.in(1 + i) <> rocc.io.autl
+      dcPorts += dcIF.io.cache
+      uncachedArbPorts += rocc.io.autl
       rocc
     }
 
@@ -108,8 +94,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       }
     }
 
-    ptw.io.requestor.drop(2) <> roccs.flatMap(_.io.ptw)
-
     core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
     core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
     respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
@@ -126,8 +110,29 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       }
     }
 
-    roccs.flatMap(_.io.utl) :+ uncachedArb.io.out
-  } else { Seq(icache.io.mem) })
+    ptwPorts ++= roccs.flatMap(_.io.ptw)
+    uncachedPorts ++= roccs.flatMap(_.io.utl)
+  }
+
+  val uncachedArb = Module(new ClientTileLinkIOArbiter(uncachedArbPorts.size))
+  uncachedArb.io.in <> uncachedArbPorts
+  uncachedArb.io.out +=: uncachedPorts
+
+  // Connect the caches and RoCC to the outer memory system
+  io.uncached <> uncachedPorts
+  io.cached <> cachedPorts
+  // TODO remove nCached/nUncachedTileLinkPorts parameters and these assertions
+  require(uncachedPorts.size == nUncachedTileLinkPorts)
+  require(cachedPorts.size == nCachedTileLinkPorts)
+
+  val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
+  ptw.io.requestor <> ptwPorts
+  ptw.io.mem +=: dcPorts
+  core.io.ptw <> ptw.io.dpath
+
+  val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
+  dcArb.io.requestor <> dcPorts
+  dcache.io.cpu <> dcArb.io.mem
 
   if (!usingRocc || nFPUPorts == 0) {
     fpuOpt.foreach { fpu =>